PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853011
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
F
EATURES
•
2 differential 2.5V/3.3V LVPECL / ECL outputs
•
1 differential PCLK, nPCLK input pair
•
PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
•
Maximum output frequency: 3GHz (typical)
•
Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
•
Output skew: 5ps (typical)
•
Part-to-part skew: 130ps (typical)
•
Propagation delay: 240ps (typical)
•
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -2.375V to -3.8V
•
-40°C to 85°C ambient operating temperature
•
Pin compatible with MC100LVEP11 and SY100EP11U
G
ENERAL
D
ESCRIPTION
The ICS853011 is a low skew, high perfor-
mance 1-to-2 Differential-to-2.5V/3.3V LVPECL/
HiPerClockS™
ECL Fanout Buffer and a member of the
HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS853011
is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853011 ideal for those
clock distribution applications demanding well defined
performance and repeatability.
,&6
B
LOCK
D
IAGRAM
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
1
2
3
4
8
7
6
5
Vcc
PCLK
nPCLK
V
EE
ICS853011
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853011AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 13, 2002
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853011
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
Type
Output
Output
Power
Input
Input
Power
Pulldown
Description
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
Clock input. V
CC
/2 default when left floating. LVPECL interface levels.
Clock input. Default LOW when left floating. LVPECL interface levels.
Positive supply pin.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5
6
7
8
Name
Q0, nQ0
Q1, nQ1
V
EE
nPCLK
PCLK
V
CC
NOTE:
Pullup
and
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLDOWN
Parameter
Input Pulldown Resistor
Test Conditions
Minimum
Typical
75
Maximum
Units
KΩ
853011AM
www.icst.com/products/hiperclocks.html
2
REV. A NOVEMBER 13, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853011
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
4.6V
-4.6V
-0.5V to V
CC
+ 0.5 V
0.5V to V
EE
- 0.5V
-65°C to 150°C
112°C/W (0 lfpm)
41°C/W to 44°C/W
265°C
NOTE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
Outputs, V
O
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40°C to +85°C
Package Thermal Impedance,
θ
JC
(Junction-to-Case)
Wave Solder, T
SOL
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V; V
EE
= 0V
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.8
25
Units
V
mA
T
ABLE
4B. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V; V
EE
= 0V
Symbol
V
OH
V
OL
V
SWING
V
PP
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
-40°C
Min
Typ
Max
Min
25°C
Typ
V
CC
- 0.9
V
CC
- 1.7
800
Max
Min
85°C
Typ
Max
Units
V
V
V
Peak-to-Peak Input Voltage
0.15
V
Input High Voltage
V
V
EE
+ 1.2
V
CMR
Common Mode Range; NOTE 2, 3
PCLK
I
IH
Input High Current
150
µA
nPCLK
PCLK
-5
I
IL
Input Low Current
µA
nPCLK
-150
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has
been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than
500 lfpm is maintained.
NOTE: Input and output parameters var y 1:1 with V
CC
. V
EE
can var y +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
853011AM
www.icst.com/products/hiperclocks.html
3
REV. A NOVEMBER 13, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853011
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
-40°C
Min
Typ
Max
Min
25°C
Typ
V
CC
- 0.9
V
CC
-1.7
0.8
Max
Min
85°C
Typ
Max
T
ABLE
3C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.5V; V
EE
= 0V
Symbol
V
OH
V
OL
V
SWING
V
PP
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Units
V
V
V
Peak-to-Peak Input Voltage
0.15
V
Input High Voltage
V
V
EE
+ 1.2
V
CMR
Common Mode Range; NOTE 2, 3
PCLK
I
IH
Input High Current
150
µA
nPCLK
PCLK
-5
I
IL
Input Low Current
µA
nPCLK
-150
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has
been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than
500 lfpm is maintained.
NOTE: Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.125V to -1.3V.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
T
ABLE
3D. ECL DC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -3.8V
TO
-2.375V
Symbol
V
OH
V
OL
V
SWING
V
PP
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
-40°C
Min
Typ
Max
Min
25°C
Typ
V
CC
- 0.9
V
CC
- 1.7
0.8
Max
Min
85°C
Typ
Max
Units
V
V
V
Peak-to-Peak Input Voltage
0.15
V
Input High Voltage
V
V
CC
+ 1.2
V
CMR
Common Mode Range; NOTE 2, 3
PCLK
I
IH
Input High Current
150
µA
nPCLK
PCLK
-5
I
IL
Input Low Current
µA
nPCLK
-150
NOTE: LVEP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has
been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than
500 lfpm is maintained.
NOTE: Input and output parameters vary 1:1 with V
CC
.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK, nPCLK is V
CC
+ 0.3V.
853011AM
www.icst.com/products/hiperclocks.html
4
REV. A NOVEMBER 13, 2002
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853011
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-2.5V/3.3V LVPECL/ECL F
ANOUT
B
UFFER
OR
T
ABLE
4. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -3.8V
TO
-2.375V
Symbol
f
MAX
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise/Fall Time
20% to 80%
Min
V
CC
= 2.375
TO
3.8V; V
EE
= 0V
-40°C
Typ
Max
Min
25°C
Typ
TBD
5
120
20
130
Max
3
Min
85°C
Typ
Max
Units
GHz
ps
ps
ps
ps
t
PD
t
sk(o)
t
sk(pp)
t
R
/t
F
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853011AM
www.icst.com/products/hiperclocks.html
5
REV. A NOVEMBER 13, 2002
京公网安备 11010802033920号
EEWORLD
