K7N163601A
K7N161801A
512Kx36 & 1Mx18 Pipelined NtRAM
TM
18Mb
TM
NtRAM
Specification
100 TQFP with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or simi-
lar applications where Product failure couldresult in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 3.0 November 2003
K7N163601A
K7N161801A
Document Title
512Kx36 & 1Mx18 Pipelined NtRAM
TM
512Kx36 & 1Mx18-Bit Pipelined NtRAM
TM
Revision History
Rev. No.
0.0
0.1
0.2
0.3
History
1. Initial document.
1. Add JTAG Scan Order
1. Add x32 org and industrial temperature .
2. Add 165FBGA package
1. Speed bin merge.
From K7N1636(32/18)09A to K7N1636(32/18)01A.
2. AC parameter change.
tOH(min)/tLZC(min) from 0.8 to 1.5 at -25
tOH(min)/tLZC(min) from 1.0 to 1.5 at -22
tOH(min)/tLZC(min) from 1.0 to 1.5 at -20
1. Final spec release.
1. Release Icc on page 14.
part #
-25
-22
-20
-16
-13
2.1
From
440
400
370
340
280
To
470
430
400
350
290
April. 04. 2003
Final
Draft Date
Remark
March. 21. 2001 Preliminary
May. 10. 2001 Preliminary
Aug. 30. 2001 Preliminary
Dec.
26. 2001 Preliminary
1.0
2.0
May. 10 .2002
May. 22. 2002
Final
Final
1. Delete 119BGA package.
2. Correct the Ball Size of 165 FBGA.
1. Delete x32 Org.
2. Delete the 225MHz speed bin
3.0
Nov. 17, 2003
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-2-
Rev. 3.0 November 2003
K7N163601A
K7N161801A
512Kx36 & 1Mx18 Pipelined NtRAM
TM
16Mb NtRAM(Flow Through / Pipelined) Ordering Informa
tion
Org.
Part Number
K7M161825A-QC(I)65/75
1Mx18 K7N161801A-Q(F)C(I)25/20/16/13
K7N161845A-Q(F)C(I)25/20/16/13
K7M163625A-QC(I)65/75
512Kx36 K7N163601A-Q(F)C(I)25/20/16/13
K7N163645A-Q(F)C(I)25/20/16/13
Mode
FlowThrough
Pipelined
Pipelined
FlowThrough
Pipelined
Pipelined
VDD
3.3
3.3
2.5
3.3
3.3
2.5
Speed
FT ; Access Time(ns)
Pipelined ; Cycle Time(MHz)
6.5/7.5 ns
250/200/167/133MHz
250/200/167/133MHz
6.5/7.5 ns
250/200/167/133MHz
250/200/167/133MHz
Q : 100TQFP
F : 165FBGA
PKG
Temp
C
; Commercial
Temp.Range
I
; Industrial
Temp.Range
-3-
Rev. 3.0 November 2003
K7N163601A
K7N161801A
512Kx36 & 1Mx18 Pipelined NtRAM
TM
512Kx36 & 1Mx18-Bit Pipelined NtRAM
TM
FEATURES
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data-
contention .
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• 100-TQFP-1420A
• 165FBGA(11x15 ball aray) with body size of 13mmx15mm.
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7N163601A and K7N161801A are 18,874,368-bits Syn-
chronous Static SRAMs.
The NtRAM
TM
, or No Turnaround Random Access Memory uti-
lizes all the bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily
stored by an edge triggered output register and then released
to the output buffers at the next rising edge of clock.
The K7N163601A and K7N161801A are implemented with
SAMSUNG′s high performance CMOS technology and is avail-
able in 100pin TQFP and 165FBGA packages. Multiple power
and ground pins minimize ground bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol -25
tCYC
tCD
tOE
4.0
2.6
2.6
-20
5.0
3.2
3.2
-16
6.0
3.5
3.5
-13
7.5
4.2
4.2
Unit
ns
ns
ns
LOGIC BLOCK DIAGRAM
LBO
ADDRESS
REGISTER
A
2
~A
18
or A
2
~A
19
A
0
~A
1
BURST
ADDRESS
COUNTER
A′
0
~A′
1
512Kx36, 1Mx18
MEMORY
ARRAY
A [0:18]or
A [0:19]
CLK
CKE
K
WRITE
ADDRESS
REGISTER
WRITE
ADDRESS
REGISTER
CONTROL
LOGIC
K
DATA-IN
REGISTER
DATA-IN
REGISTER
K
CS
1
CS
2
CS
2
ADV
WE
BW
x
(x=a,b,c,d or a,b)
OE
ZZ
DQa
0
~ DQd
7
or DQa
0
~ DQb
8
DQPa ~ DQPd
36 or 18
CONTROL
REGISTER
CONTROL
LOGIC
K
OUTPUT
REGISTER
BUFFER
NtRAM
TM
and No Turnaround Random Access Memory are trademarks of Samsung.
-4-
Rev. 3.0 November 2003
K7N163601A
K7N161801A
PIN CONFIGURATION
(TOP VIEW)
BWd
BWb
BWa
BWc
512Kx36 & 1Mx18 Pipelined NtRAM
TM
ADV
CKE
CLK
CS
1
CS
2
CS
2
V
DD
V
SS
WE
A
18
A
17
83
OE
A
6
A
7
A
8
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
A
5
A
4
A
3
A
2
A
1
A
0
A
10
A
12
A
13
A
14
A
15
N.C.
N.C.
V
DD
N.C.
LBO
N.C.
V
SS
PIN NAME
SYMBOL
A
0
- A
18
PIN NAME
Address Inputs
TQFP PIN NO.
32,33,34,35,36,37,44
45,46,47,48,49,50,81
82,83,84,99,100
85
88
89
87
98
97
92
93,94,95,96
86
64
31
SYMBOL
V
DD
V
SS
N.C.
DQa
0
~a
7
DQb
0
~b
7
DQc
0
~c
7
DQd
0
~d
7
DQPa~P
d
or NC
V
DDQ
V
SSQ
PIN NAME
TQFP PIN NO.
Power Supply(+3.3V) 14,15,16,41,65,66,91
17,40,67,90
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
38,39,42,43
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
ADV
WE
CLK
CKE
CS
1
CS
2
CS
2
BWx(x=a,b,c,d)
OE
ZZ
LBO
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
A
11
Output Power Supply 4,11,20,27,54,61,70,77
(3.3V or 2.5V)
5,10,21,26,55,60,71,76
Output Ground
Note :
1. A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
-5-
Rev. 3.0 November 2003
A
16
50
NC/DQPc
DQc
0
DQc
1
V
DDQ
V
SSQ
DQc
2
DQc
3
DQc
4
DQc
5
V
SSQ
V
DDQ
DQc
6
DQc
7
V
DD
V
DD
V
DD
V
SS
DQd
0
DQd
1
V
DDQ
V
SSQ
DQd
2
DQd
3
DQd
4
DQd
5
V
SSQ
V
DDQ
DQd
6
DQd
7
NC/DQPd
81
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
K7N163601A(512Kx36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb
7
DQb
6
V
DDQ
V
SSQ
DQb
5
DQb
4
DQb
3
DQb
2
V
SSQ
V
DDQ
DQb
1
DQb
0
V
SS
V
DD
V
DD
ZZ
DQa
7
DQa
6
V
DDQ
V
SSQ
DQa
5
DQa
4
DQa
3
DQa
2
V
SSQ
V
DDQ
DQa
1
DQa
0
DQPa/NC
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