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DM74ALS253M

Description
3-STATE Dual 1-of-4 Line Data Selector/Multiplexer
Categorylogic    logic   
File Size49KB,5 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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DM74ALS253M Overview

3-STATE Dual 1-of-4 Line Data Selector/Multiplexer

DM74ALS253M Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeSOIC
package instructionSOP, SOP16,.25
Contacts16
Reach Compliance Codeunknow
seriesALS
JESD-30 codeR-PDSO-G16
JESD-609 codee3
length9.9 mm
Logic integrated circuit typeMULTIPLEXER
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of functions2
Number of entries4
Output times1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
power supply5 V
Maximum supply current (ICC)14 mA
Prop。Delay @ Nom-Su14 ns
propagation delay (tpd)14 ns
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9 mm
DM74ALS253 3-STATE Dual 1-of-4 Line Data Selector/Multiplexer
April 1984
Revised February 2000
DM74ALS253
3-STATE Dual 1-of-4 Line Data Selector/Multiplexer
General Description
This Data Selector/Multiplexer contains full on-chip decod-
ing to select one-of-four data sources as a result of a
unique two-bit binary code at the Select Inputs. Each of the
two Data Selector/Multiplexer circuits have their own sepa-
rate Data and Output Control inputs and a non-inverting 3-
STATE output buffer. The Output Control inputs, when at
the high level, place the corresponding output in the high
impedance OFF-State. In order to prevent bus access con-
flicts, output disable times are shorter than output enable
times. The Select input buffers incorporate internal overlap
features to ensure that select input changes do not cause
invalid output transients.
Features
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
Switching performance is guaranteed over full tempera-
ture and V
CC
supply range
s
Pin and functional compatible with LS family counterpart
s
Improved output transient handling capability
s
Output control circuitry incorporates power-up 3-STATE
feature
Ordering Code:
Order Number
DM74ALS253M
DM74ALS253N
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Select
Inputs
B
X
L
L
L
L
H
H
H
H
A
X
L
L
H
H
L
L
H
H
C0
X
L
H
X
X
X
X
X
X
C1
X
X
X
L
H
X
X
X
X
C2
X
X
X
X
X
L
H
X
X
C3
X
X
X
X
X
X
X
L
H
Data Inputs
Output
Control
G
H
L
L
L
L
L
L
L
L
Y
Z
L
H
L
H
L
H
L
H
Output
Address inputs A and B are common to both sections
H
=
HIGH Level
L
=
LOW Level
X
=
Don't Care
Z
=
High Impedance
© 2000 Fairchild Semiconductor Corporation
DS006215
www.fairchildsemi.com

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