Voltage on any other Pin . . . . . . . . . . . . . . . . . . . . . . . . . V
CC
± 0.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty
NOTE:
1.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
.
Conditions are as follows, unless otherwise specified. All typical values are for T
A
= +25°C and 5V at pin V
CC
.
Maximum and minimum specifications are over the recommended operating conditions. All voltages are
referred to the voltage at pin V
SS
. All bits in control registers are “0”. 255Ω, 0.1%, resistor connected between
R
1
and V
SS
, and another between R
2
and V
SS
. 400kHz TTL input at SCL. SDA pulled to V
CC
through an
external 2kΩ resistor. 2-wire interface in “standby” (see Notes 9 and 10 on page 5). WP, A0, A1, and A2 floating.
V
REF
pin unloaded.
TEST CONDITIONS
R
1
and R
2
floating, V
REF
unloaded.
2-wire interface reading from
memory, I
1
and I
2
both connected to V
SS
,
DAC input bytes: FFh, V
REF
unloaded.
Average from START condition until t
WP
after the STOP condition
WP: V
CC
, R
1
and R
2
Floating, V
REF
unloaded.
0
4
MIN
(Note 3)
TYP
MAX
(Note 3)
2
15
UNIT
mA
mA
SYMBOL
Iccstby
Iccfull
PARAMETER
Stand-by Current into V
CC
Pin
Full Operation Current into V
CC
Pin
Nonvolatile Write Current into
V
CC
Pin
Iccwrite
mA
I
PLDN
V
ILTTL
V
IHTTL
I
INTTL
V
OLSDA
I
OHSDA
V
ILCMOS
V
IHCMOS
VRefout
RV
REF
TCOref
VRef Range
TSenseRange
TSenseAccuracy
On-chip Pull-down Current at WP, V(WP), V(A0), V(A1), and V(A2) from 0V
A0, A1, and A2
to V
CC
SCL and SDA, Input Low Voltage
SCL and SDA, Input High Voltage
SCL and SDA Input Current
SDA Output Low Voltage
SDA Output High Current
WP, A0, A1, and A2 Input Low
Voltage
WP, A0, A1, and A2 Input High
Voltage
Output Voltage at V
REF
at +25°C
VREF Pin Input Resistance
Temperature Coefficient of V
REF
Output Voltage
Voltage Range when V
REF
is an
Input
Temperature Sensor Range
Temperature Sensor Accuracy
-20µA
≤
I(V
REF
)
≤
20µA
VRM bit = “1”, +25°C
Notes 2 and 8
Note 6
Note 2
Pin voltage between 0 and V
CC
, and SDA
as an input.
I(SDA) = 2mA
V(SDA) = V
CC
1
20
0.8
µA
V
V
2.0
-1
0
0
0
0.8 x V
CC
1.205
20
-100
1
-40
+/-2
1.21
10
0.4
100
0.2 x V
CC
V
CC
1.215
40
+100
1.3
100
µA
V
µA
V
V
V
kΩ
ppm/°C
V
°C
°C
3
FN8216.3
February 20, 2008
X96012
Electrical Specifications
Conditions are as follows, unless otherwise specified. All typical values are for T
A
= +25°C and 5V at pin V
CC
.
Maximum and minimum specifications are over the recommended operating conditions. All voltages are
referred to the voltage at pin V
SS
. All bits in control registers are “0”. 255Ω, 0.1%, resistor connected between
R
1
and V
SS
, and another between R
2
and V
SS
. 400kHz TTL input at SCL. SDA pulled to V
CC
through an
external 2kΩ resistor. 2-wire interface in “standby” (see Notes 9 and 10 on page 5). WP, A0, A1, and A2 floating.
V
REF
pin unloaded.
(Continued)
TEST CONDITIONS
MIN
(Note 3)
0
1.5
0.2
Figure 11
2.6
TYP
MAX
(Note 3)
3200
2.8
50
2.8
UNIT
µA
V
mV/µs
V
SYMBOL
I
R
V
POR
V
CC
Ramp
V
ADCOK
NOTES:
PARAMETER
Current from pin R1 or R2 to VSS
Power-on Reset Threshold
Voltage
V
CC
Ramp Rate
ADC Enable Minimum Voltage
2. These parameters are periodically sampled and not 100% tested.
3. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
4. The device goes into Standby: 200ns after any STOP, except those that initiate a nonvolatile write cycle. It goes into Standby t
WC
after a STOP
that initiates a nonvolatile write cycle. It also goes into Standby 9 clock cycles after any START that is not followed by the correct Slave Address
Byte.
5. t
WC
is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
6. For this range of V(V
REF
) the full scale sink mode current at I1 and I2 follows V(V
REF
) with a linearity error smaller than 1%.
7. These parameters are periodically sampled and not 100% tested.
8. TCO
ref
= [Max V(V
REF
) - Min V(V
REF
)] x 10
6
/(1.21V x +140°C).
D/A Converter Characteristics
(See “Electrical Specifications” table starting on page 3 for standard conditions).
SYMBOL
IFS
00
PARAMETER
TEST CONDITIONS
MIN
(Note 3)
1.56
TYP
1.58
MAX
(Note 3)
1.6
3.2
0.3
0.64
1
1
-2
-0.5
-1
0.4
0.85
1.3
0.5
1.06
1.6
1
2
0.5
1
UNIT
mA
mA
mA
mA
mA
LSB
LSB
LSB
LSB
I1 or I2 Full Scale Current, with External Resistor (Notes 9, 12)
Setting
(Notes 2, 9, 13)
I1 or I2 Full Scale Current, with Internal Low
Current Setting Option
I1 or I2 Full Scale Current, with Internal Middle
Current Setting Option
I1 or I2 Full Scale Current, with Internal High
Current Setting Option
I1 or I2 D/A Converter Offset Error
I1 or I2 D/A Converter Full Scale Error
I1 or I2 D/A Converter Differential Nonlinearity
I1 or I2 D/A Converter Integral Nonlinearity with
Respect to a Straight Line Through 0 and the Full
Scale Value
I1 or I2 Sink Voltage Compliance
(Note 12)
(Notes 2, 13)
DAC input Byte = FFh,
Source or sink mode, V(I1) and V(I2)
are V
CC
- 1.2V in source mode and
1.2V in sink mode.
(Notes 10, 11)
IFS
01
IFS
10
IFS
11
Offset
DAC
FSError
DAC
DNL
DAC
INL
DAC
V
ISink
1.2
2.5
0
0
V
CC
V
CC
V
CC
- 1.2
V
CC
- 2.5
V
V
V
V
V
ISource
I1 or I2 Source Voltage Compliance
(Note 12)
(Notes 2, 13)
4
FN8216.3
February 20, 2008
X96012
D/A Converter Characteristics
(See “Electrical Specifications” table starting on page 3 for standard conditions).
(Continued)
SYMBOL
I
OVER
I
UNDER
t
rDAC
TCO
I1I2
PARAMETER
I1 or I2 Overshoot on D/A Converter Data Byte
Transition
I1 or I2 Undershoot on D/A Converter Data Byte
Transition
I1 or I2 Rise Time on D/A Converter Data Byte
Transition; 10% to 90%
Temperature Coefficient of Output Current I1 or
I2 when Using Internal Resistor Setting
Bits I1FSO[1:0] ¦ 00
2
or
Bits I2FSO[1:0] ¦ 002,
VRMbit = “1”
See Figure 8
TEST CONDITIONS
DAC input byte changing from 00h to
FFh and vice versa, V(I1) and V(I2)
are V
CC
- 1.2V in source mode and
1.2V in sink mode. (Note 2)
5
±200
MIN
(Note 3)
TYP
MAX
(Note 3)
0
0
30
UNIT
µA
µA
µs
ppm/°C
NOTES:
9. DAC input Byte = FFh, Source or sink mode.
2 V(VRef)
10. LSB is defined as
divided by the resistance between R
1
or R
2
to V
SS
.
x
255
3
11. Offset
DAC
: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is expressed in
LSB. FSError
DAC
: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It is
expressed in LSB. The Offset
DAC
is subtracted from the measured value before calculating FSError
DAC
.DNL
DAC
: The Differential Non-Linearity of
a DAC is defined as the deviation between the measured and ideal incremental change in the output of the DAC, when the input changes by one
code step. It is expressed in LSB. The measured values are adjusted for Offset and Full Scale Error before calculating DNL
DAC
. INL
DAC
: The
Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjusting the measured transfer
curve for Offset and Full Scale Error. It is expressed in LSB.
[
]
12. V(I1) and V(I2) are V
CC
- 1.2V in source mode and 1.2V in sink mode. In this range the current at I1 or I2 varies < 1%.
13. The maximum current, sink or source, can be set with an external resistor to 3.2 mA with a minimum V
CC
= 4.5V. The compliance
voltage changes to 2.5V from the sourcing rail, and the current variation is < 1%.
.
A/D Converter Characteristics
(See “Electrical Specifications” table starting on page 3 for standard conditions).
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