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SI52142-A01AGM

Description
PCI Express(PCIe) 时钟/频率发生器,扇出缓冲器(分配),多路复用器 IC 200MHz 1 输出 24-QFN(4x4)
Categorysemiconductor    clock and timing   
File Size2MB,23 Pages
ManufacturerSkyworks
Websitehttp://www.skyworksinc.com
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SI52142-A01AGM Overview

PCI Express(PCIe) 时钟/频率发生器,扇出缓冲器(分配),多路复用器 IC 200MHz 1 输出 24-QFN(4x4)

SI52142-A01AGM Parametric

Parameter NameAttribute value
category
MakerSkyworks
series-
Packagetray
PLLyes
The main purposePCI Express(PCIe)
enterclock, crystal
outputHCSL
Number of circuits1
Ratio - Input:Output1:3
Differential - Input:OutputNo/Yes
Frequency - maximum200MHz
Voltage - Power supply3.135V ~ 3.465V
Operating temperature-40°C ~ 85°C
Installation typesurface mount type
Package/casing24-WFQFN Exposed Pad
Supplier device packaging24-QFN(4x4)
Basic product numberSI52142
Si 52142xx
PC I- E
XPRESS
G
EN
1 , G
EN
2 , & G
E N
3 T
WO
-O
UTP UT
C
L OCK
G
ENERATOR WITH
2 5 MH
Z
R
E F E R E N C E
C
LOCK
Features
PCI-Express Gen 1, Gen 2, Gen 3,
and Gen 4 common clock compliant
Gen 3 SRNS Compliant
Two 100 MHz, 125 MHz, or 200 MHz
differential clock outputs
Supports Serial ATA (SATA) at
100 MHz
Low power, push-pull HCSL
compatible differential outputs
No termination resistors required
Dedicated output enable hardware
pins for each clock output
Dedicated hardware pins for spread
spectrum and frequency control on
differential outputs
Up to two PCI-Express clocks
25 MHz reference clock output
25 MHz crystal input or clock input
Signal integrity tuning
I
2
C support with readback
capabilities
Triangular spread spectrum profile
for maximum electromagnetic
interference (EMI) reduction
Industrial temperature
–40 to 85 °C
3.3 V power supply
24-pin QFN package
Ordering Information:
See page 18.
Pin Assignments
Applications
Network attached storage
Multi-function printer
Wireless access point
Routers
VDD_REF
REF
1
2
3
4
5
6
VDD_CORE
VSS_CORE
XIN/CLKIN
SDATA
20
24
23
22
XOUT
21
Description
The Si52142 is a spread-spectrum enabled PCIe clock generator that can source
two PCIe clocks and a 25 MHz reference clock. The device has three hardware
output enable pins for enabling the respective outputs, and two hardware pins to
control spread spectrum and frequency on PCIe clock outputs. In addition to the
hardware control pins, I
2
C programmability is also available to dynamically control
skew, edge rate, and amplitude on the true, compliment, or both differential
signals on the PCIe clock outputs. This control feature enables optimal signal
integrity as well as optimal EMI signature on the PCIe clock outputs.
Refer to AN636 for signal integrity and configurability. Measuring PCIe clock jitter
is quick and easy with the Skyworks Solutions PCIe Clock Jitter Tool. Download it
for free at
https://www.skyworksinc.com/en/application-pages/pci-express-learn-
ing-center.
SCLK
19
1
18 OE_DIFF1
17 VDD_DIFF
16 DIFF1
15 DIFF1
14 DIFF0
13 DIFF0
7
8
9
10
11
12
OE_REF
1
VSS_REF
OE_DIFF0
1
VDD_DIFF
25
GND
NC
NC
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
Patents pending
Functional Block Diagram
XIN/CLKIN
XOUT
REF
DIFF0
PLL1
(SSC)
Divider
DIFF1
SCLK
SDATA
OE_REF
OE [1:0]
SS [1:0]
Control & Memory
Control
RAM
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 23, 2021
VDD_DIFF
SS0
2
SS1
NC
2
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