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SI53312-B-GM

Description
时钟 扇出缓冲器(分配),多路复用器,变换器 IC 2:10 1.25 GHz 44-VFQFN 裸露焊盘
Categorysemiconductor    clock and timing   
File Size2MB,33 Pages
ManufacturerSkyworks
Websitehttp://www.skyworksinc.com
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SI53312-B-GM Overview

时钟 扇出缓冲器(分配),多路复用器,变换器 IC 2:10 1.25 GHz 44-VFQFN 裸露焊盘

SI53312-B-GM Parametric

Parameter NameAttribute value
category
MakerSkyworks
series-
Packagetray
typefanout buffers (distribution), multiplexers, converters
Number of circuits1
Ratio - Input:Output2:10
Differential - Input:OutputYes Yes
enterCML,HCSL,LVCMOS,LVDS,LVPECL
outputCML,HCSL,LVCMOS,LVDS,LVPECL
Frequency - maximum1.25 GHz
Voltage - Power supply1.71V ~ 3.63V
Operating temperature-40°C ~ 85°C
Installation typesurface mount type
Package/casing44-VFQFN Exposed Pad
Supplier device packaging44-QFN(7x7)
Basic product numberSI53312
Si53312
1 : 1 0 L
O W
J
I T T E R
U
N IV ER SA L
B
U F F E R
/ L
EVEL
T
R A N S L ATO R W I T H
2 : 1 I
N PU T
M
UX
( < 1 . 2 5 G H
Z
)
Features
10 differential or 20 LVCMOS outputs
Ultra-low additive jitter: 45 fs rms
Wide frequency range:
dc to 1.25 GHz
Any-format input with pin selectable
output formats: LVPECL, Low Power
LVPECL, LVDS, CML, HCSL,
LVCMOS
2:1 mux with hot-swappable inputs
Asynchronous output enable
Output clock division: /1, /2, /4
(/2 and /4 for dc to 725 MHz)
Low output-output skew: <70 ps
Low propagation delay variation:
<400 ps
Independent V
DD
and V
DDO
:
1.8/2.5/3.3 V
Excellent power supply noise
rejection (PSRR)
Selectable LVCMOS drive strength to
tailor jitter and EMI performance
Small size: 44-QFN (7 mm x 7 mm)
RoHS compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Ordering Information:
See page 28.
Applications
Pin Assignments
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
DIVA
1
2
3
4
5
6
7
8
9
10
11
Si53312
VDDOA
VDDOB
34
Q3
Q3
Q4
Q4
GND
Q5
Q5
43
42
41
40
39
38
37
Q6
Q6
36
35
44
33
32
31
30
DIVB
SFOUTB[1]
SFOUTB[0]
Q7
Q7
NC
Q8
Q8
Q9
Q9
CLK_SEL
Description
The Si53312 is an ultra low jitter ten output differential buffer with pin-selectable
output clock signal format and divider selection. The Si53312 features a 2:1 mux,
making it ideal for redundant clocking applications. The Si53312 utilizes Skyworks
Solutions' advanced CMOS technology to fanout clocks from dc to 1.25 GHz with
guaranteed low additive jitter, low skew, and low propagation delay variability. The
Si53312 features minimal cross-talk and provides superior supply noise rejection,
simplifying low jitter clock distribution in noisy environments. Independent core
and output bank supply pins provide integrated level translation without the need
for external circuitry.
SFOUTA[1]
SFOUTA[0]
Q2
Q2
GND
Q1
Q1
Q0
GND
PAD
29
28
27
26
25
24
23
Q0
NC
12
15
16
13
17
19
20
14
18
21
VDD
CLK0
CLK0
OEA
V
REF
OEB
CLK1
Patents pending
Functional Block Diagram
Power
Supply
Filtering
V
REF
Vref
Generator
DIVA
VDDOA
SFOUTA[1:0]
OEA
Q0, Q1, Q2, Q3, Q4
DivA
CLK0
/CLK0
Q0, Q1, Q2, Q3, Q4
DIVB
CLK1
/CLK1
DivB
CLK_SEL
Switching
Logic
Q5, Q6, Q7, Q8, Q9
VDDOB
SFOUTB[1:0]
OEB
Q5, Q6, Q7, Q8, Q9
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • September 3, 2021
CLK1
NC
GND
NC
22
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