SL2304NZ
Not Recommended for New Designs
Low Jitter and Skew DC to 140MHz Clock Buffer
Key Features
DC to 140 MHz operating frequency range
Low output clock skew: 50ps-typ
Low part-to-part output skew: 100 ps-typ
Low output propogation delay: 2.5ns-typ
3.3V +/-10% operation supply voltage
Description
The SL2304NZ is a low skew, jitter and power fanout
Buffer designed to produce up to four (4) clock outputs
from one (1) reference input clock, for high speed clock
distribution, including PCI/PCI-X applications.
The SL2304NZ products operate from DC to 140MHz.
N
ot
fo R
r N ec
om
ew
m
D e
es nd
ig e
ns d
Low power dissipation:
- 7 mA-typ at 33MHz
- 9 mA-typ at 66MHz
- 12 mA-typ at 133MHz
One input to four output fanout buffer drivers
Output Enable (OE) control function
Available in 8-pin TSSOP package
The only difference between SL2304NZ-1 and SL2304NZ-
1Z is the OE logic implementation. Refer to the Available
OE Logic Configuration Table. 1
Refer to SL23EP04NZ products for DC to 220MHz-max
frequency range and 2.5V to 3.3V power supply operation,
improved skew, jitter and higher drive options.
Benefits
Available in Commercial and Industrial grades
Available in Lead (Pb) free package
Applications
General Purpose PCI/PCI-X Clock Buffer
Printers, MFPs and Digital Copiers
PCs and Work Stations
Routers, Switches and Servers
Datacom and Telecom
High-Speed Digital Embeded Systems
Up to four (4) distribution of input clock
Low propogation delay
Low output-to-output skew
Low output clock Jitter
Low power dissipation
Block Diagram
OE
Logic
Control
CLK1
CLK2
CLKIN
CLK3
CLK4
VDD
GND
Rev 2.1, May 6, 2008
Page 1 of 9
2400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL2304NZ
Pin Configuration
CLKIN
OE
1
2
3
4
8
7
CLK4
CLK3
VDD
N
ot
fo R
r N ec
om
ew
m
D e
es nd
ig e
ns d
CLK1
GND
6
5
CLK2
8-Pin TSSOP
Pin Description
Pin
Number
1
2
3
4
5
6
7
8
Pin Name
CLKIN
OE
Pin Type
Input
Pin Description
Reference Clock Input
Output
Output
Power
Output
Output
Power
Input
Output Enable. Refer to the Table. 1 for Logic Table
Buffered Clock Output 1
Power Ground.
CLK1
GND
VDD
CLK2
CLK3
CLK4
Buffered Clock Output 2
3.3V Power Supply
Buffered Clock Output 3
Buffered Clock Output 4
Rev 2.1, May 6, 2008
Page 2 of 9
SL2304NZ
General Description
The SL2304NZ is a low skew, jitter and power fanout
Buffer designed to produce up to four (4) clock outputs
from one (1) reference input clock, for high speed clock
distribution, including PCI/PCI-X applications.
Output Clock Skew
All outputs should drive the similar load to achieve output-
to-output skew and input-to-output delay specifications as
given in the switching electrical tables.
N
ot
fo R
r N ec
om
ew
m
D e
es nd
ig e
ns d
The input and output frequency is the same (1x) for
SL2304NZ-1 and SL2304NZ-1Z and operates from DC
to 140MHz clock range with up to 25pF output load.
Input and output Frequency Range
Power Supply Range (VDD)
OE (Output Enable) Function
The SL2304NZ is designed to operate 3.3V+/-10% (3.63V-
max to 2.97V-min) VDD power supply range. An internal
on-chip voltage regulator is used to provide to constant
power supply of 1.8V, leading to a consistent and stable
electrical performance in terms of skew and jitter. The
SL2304NZ I/O is powered by using VDD.
Refer to SL23EP04NZ products for DC to 220MHz-max
frequency range, 2.5V to 3.3V power supply operation,
improved skew, jitter and higher drive options.
Contact SLI for 1.8V power supply Fan-Out Buffer and
ZDB products.
The only difference between SL2304-1 and SL2304NZ-
1Z is the OE logic implementation. When OE=0,
SL2404NZ-1 outputs are disabled and outputs are at
Logic Low. In the case of SL2304NZ-1Z the outputs are
at High-Z. Refer to the Available OE Logic Configuration
Table. 1 below.
CLKIN (Pin-1)
Low
Low
OE (Pin-2)
Low
Low
SL2304NZ-1
CLKOUT [1:4]
Low
Low
Low
SL2304NZ-1Z
CLKOUT [1:4]
High-Z
High-Z
Low
High
High
High
High
High
High
Table 1. Available SL2304 CLKIN and OE Logic Configurations
Rev 2.1, May 6, 2008
Page 3 of 9
SL2304NZ
Absolute Maximum Ratings (All Products)
Description
Supply voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Ambient Operating Temperature
Storage Temperature
Junction Temperature
In operation, C-Grade
In operation, I-Grade
No power is applied
Condition
Min
-0.5
-0.5
0
-40
-65
–
–
Max
4.6
VDD+0.5
70
85
Unit
V
V
°C
°C
°C
°C
°C
V
V
V
N
ot
fo R
r N ec
om
ew
m
D e
es nd
ig e
ns d
150
125
260
In operation, power is applied
JEDEC22-A114D
JEDEC22-A115D
Soldering Temperature
ESD Rating (Human Body Model)
ESD Rating (Machine Model)
-4,000
-1,500
-200
4,000
1,500
200
ESD Rating (Charge Device Model)
JEDEC22-C101C
Operating Conditions (C-Grade and VDD=3.3V)
Description
Symbol
VDD
TA
VIH
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Condition
Min
0
–
–
–
Typ
3.3
–
3
–
–
–
–
Max
3.63
70
5
30
15
Unit
V
°C
Operating Voltage
VDD+/-10%
2.97
Operating Temperature
Input Capacitance
Ambient Temperature
Pins 1 and 2
All outputs≤100MHz
All outputs≤140MHz
Input Clock Range
pF
pF
pF
Output Capacitance
CL1
CL2
Input Operating Frequency
Input Operating Frequency
CLKIN
DC
DC
140
100
MHz
MHz
CLKN2
Input Clock Range, CL=30pF
Rev 2.1, May 6, 2008
Page 4 of 9
SL2304NZ
DC Electrical Characteristics (C-Grade and VDD=3.3V)
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Description
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Symbol
VINL
VINH
IINL
IINH
Condition
CLKIN and OE
CLKIN and OE
0 < VIN < 0.8V
I
OL
=24mA
I
OL
=12mA
Min
–
2.0
-5
-5
–
–
Typ
–
–
+/-2
+/-2
–
–
–
–
7
9
Max
0.8
VDD+0.3
5
5
Unit
V
V
µA
µA
V
V
V
V
N
ot
fo R
r N ec
om
ew
m
D e
es nd
ig e
ns d
2.4V < VIN < VDD
Output Low Voltage
VOL1
VOL2
0.80
0.55
–
–
Output High Voltage
VOH1
VOH1
IDD1
IDD2
IDD3
I
OH
=-24mA
I
OH
=-12mA
2.0
2.4
–
–
–
Power Supply Current
Power Supply Current
Power Supply Current
CLKIN=33MHz
CL=0 (No load at outputs)
11
14
18
CLKIN=66MHz
CL=0 (No load at outputs)
CLKIN=133MHz
CL=0 (No load at outputs)
12
mA
mA
mA
Switching Electrical Characteristics (C-Grade and VDD=3.3V)
Description
Symbol
FOUT1
FOUT1
tr/f-1
tr/f-2
DC1
DC2
DC3
Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Condition
Min
DC
DC
–
–
Typ
–
–
–
–
Max
140
100
2.0
Unit
MHz
MHz
ns
ns
%
%
%
Output Frequency Range
Output Rise/Fall Time
Output Rise/Fall Time
Input Duty Cycle
CL=15pF
CL=30pF
Measured at 0.8V to 2.0V
CL=15pF
Measured at 0.8V to 2.0V
CL=30pF
Measured at VDD/2
CL=15pF, Fout=140MHz
Measured at VDD/2
2.4
80
55
60
20
45
40
–
–
50
–
–
Output Duty Cycle
Output Duty Cycle
CL=30pF, Fout=100MHz
Measured at VDD/2
Output to Output Skew
Part to Part Skew
SKW1
SKW2
PDT
CCJ1
CCJ2
Measured at VDD/2 and
Outputs are equally loaded
Measured at VDD/2 and
Outputs are equally loaded
50
100
200
3.5
ps
ps
ns
ps
ps
100
2.5
75
50
Propagation Delay Time
Cycle-to-Cycle Jitter
Cycle-to-Cycle Jitter
Rev 2.1, May 6, 2008
Measured at VDD/2 from CLKIN to
Output Clock rising edge
CLKIN=66MHz and CL=15
CLKIN=133MHz and CL=15
1.5
–
–
150
100
Page 5 of 9
京公网安备 11010802033920号
EEWORLD
