Low Skew, 1-to-12 LVCMOS/LVTTL
Fanout Buffer
Datasheet
8312
General Description
The 8312 is a low skew, 1-to-12 LVCMOS/ LVTTL Fanout Buffer
and a member of the family of High Performance Clock Solutions
from IDT. The 8312 single-ended clock input accepts LVCMOS or
LVTTL input levels. The low impedance LVCMOS outputs are
designed to drive 50 series or parallel terminated transmission
lines. The effective fanout can be increased from 12 to 24 by
utilizing the ability of the outputs to drive two series terminated
lines.
The 8312 is characterized at full 3.3V, 2.5V, and 1.8V, mixed
3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply
modes. Guaranteed output and part-to-part skew characteristics
along with the 1.8V output capabilities makes the 8312 ideal for
high performance, single ended applications that also require a
limited output voltage.
Features
•
•
•
•
•
Twelve LVCMOS/LVTTL outputs
CLK input supports the following input types: LVCMOS, LVTTL
Maximum output frequency: 250MHz
Output skew: 150ps (maximum)
Supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
1.8V/1.8V
0°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
•
•
Block Diagram
CLK_EN
Pullup
Pin Assignment
GND
D
Q
LE
GND
V
DD
CLK_EN
12
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
9
Q11
Q1
GND
V
DDO
V
DDO
Q2
Q3
Q0
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
GND
V
DDO
V
DDO
GND
Q10
Q9
Q8
Q4
V
DDO
Q5
GND
Q6
V
DDO
Q7
GND
CLK
Pulldown
Q[0:11]
CLK
GND
OE
OE
Pullup
V
DD
GND
8312
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2015 Integrated Device Technology, Inc
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December 11, 2015
8312 Datasheet
Table 1. Pin Descriptions
Number
1, 5, 8, 12, 16,
17, 21, 25, 29
2, 7
3
4
6
9, 11, 13, 15,
18, 20, 22, 24,
26, 28, 30, 32
10, 14, 19, 23,
27, 31
Name
GND
V
DD
CLK_EN
CLK
OE
Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
V
DDO
Power
Power
Input
Input
Input
Pullup
Pulldown
Pullup
Type
Description
Power supply ground.
Positive supply pins.
Synchronous control for enabling and disabling clock outputs.
LVCMOS / LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of outputs Q[0:11].
LVCMOS / LVTTL interface levels.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output
Power
Output supply pins.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
V
DDO
= 3.465V
C
PD
Power Dissipation Capacitance
(per output)
V
DDO
= 2.625V
V
DDO
= 2V
V
DDO
= 3.3V ± 5%
R
OUT
Output Impedance
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 0.2V
7
7
10
Test Conditions
Minimum
Typical
4
51
51
19
18
16
Maximum
Units
pF
k
k
pF
pF
pF
©2015 Integrated Device Technology, Inc
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December 11, 2015
8312 Datasheet
Function Tables
Table 3A. Output Enable and Clock Enable Function Table
Inputs
OE
0
1
1
CLK_EN
X
0
1
Outputs
Q [0:11]
Hi-Z
LOW
Follows CLK input
Table 3B. Output Enable and Clock Enable Function Table
Inputs
OE
1
1
CLK_EN
1
1
CLK
0
1
Outputs
Q [0:11]
LOW
HIGH
©2015 Integrated Device Technology, Inc
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December 11, 2015
8312 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
47.9C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
10
10
Units
V
V
mA
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= 0°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
10
10
Units
V
V
mA
mA
Table 4C. Power Supply DC Characteristics,
V
DD
= V
DDO
= 1.8V ± 0.2V, T
A
= 0°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
1.6
1.6
Typical
1.8
1.8
Maximum
2.0
2.0
10
10
Units
V
V
mA
mA
©2015 Integrated Device Technology, Inc
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December 11, 2015
8312 Datasheet
Table 4D. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= 0°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
10
10
Units
V
V
mA
mA
Table 4E. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= 0°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
1.6
Typical
3.3
1.8
Maximum
3.465
2.0
10
10
Units
V
V
mA
mA
Table 4F. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= 0°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
1.6
Typical
2.5
1.8
Maximum
2.625
2.0
10
10
Units
V
V
mA
mA
©2015 Integrated Device Technology, Inc
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December 11, 2015
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