Si5330x Data Sheet
Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10
Universal Outputs from Any-Format Input and Wide Frequency
Range from 1 MHz to 725 MHz
The Si5330x family of Universal/Any-format fanout buffers is ideal for clock distribution
(1 MHz minimum) and redundant clocking applications. These devices feature typical
ultra-low jitter characteristics of 50 fs and operate over a wide frequency range. Built-in
LDOs deliver high PSRR performance and reduce the need for external components,
simplifying low-jitter clock distribution in noisy environments.
The Si5330x family is available in multiple configurations, with some versions offering
a selectable input clock using a 2:1 input mux. Other features include independent
(synchronous) output enable, glitchless switching, LOS monitor of input clocks, output
clock division, and built-in format translation. These buffers can be paired with the
Si534x clocks and jitter attenuators, the Si5332 clocks, and the Si5xx oscillators to
deliver end-to-end clock tree performance.
KEY FEATURES
• Ultra-low additive jitter: 50 fs rms
• Built-in LDOs for high PSRR performance
• Up to 10 outputs
• Any-format Inputs (LVPECL, Low-power
LVPECL, LVDS, CML, HCSL, LVCMOS)
• Wide frequency range
• Output Enable option
• Multiple configuration options
• Dual Bank option
• 2:1 Input Mux operation
• Synchronous output enable
• Loss of signal (LOS) monitors for loss of
input clock
• Output clock division: /1, /2, /4
• RoHS compliant, Pb-free
• Temperature range: –40 to +85 °C
1
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1
Si5330x Data Sheet • Ordering Guide
1. Ordering Guide
Table 1.1. Product Family Overview
Part
Number
Si53301-B-GM
Si53302-B-GM
Si53303-B-GM
Si53304-B-GM
Si53305-B-GM
Si53306-B-GM
Si53307-B-GM
Si53308-B-GM
Description
Input
MUX
Yes
Yes
No
Yes
Yes
No
Yes
No
Input
Output
Glitch-
less
Switch
1
Yes
Yes
No
Yes
Yes
No
Yes
No
LOS
Output
Yes
Yes
No
No
No
No
No
Yes
OE
Option
Per Bank
Per Bank
Per Bank
Individual
Individual
Single
Single
Per Bank
Synchro-
nous OE
1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Clk Divid-
er Option
Per Bank
Per Bank
Per Bank
No
No
No
No
Per Bank
6 output universal buffer
with 2:1 input mux
10 output universal buffer
with 2:1 input mux
Dual 1:5 universal buffer
6 output universal buffer
with 2:1 input mux
10 output universal buffer
with 2:1 input mux
4 output universal buffer,
single input
2 output universal buffer
with 2:1 input mux
Dual 1:3 universal buffer
2
2
2
2
2
1
2
2
6 Diff / 12
SE
10 Diff / 20
SE
5 Diff / 10
SE
6 Diff / 12
SE
10 Diff / 20
SE
4 Diff / 8 SE
2 Diff / 4 SE
3 Diff / 6 SE
Note:
1. The synchronous features (Glitch-less switching and Synchronous OE) of the Si533xx family require a minimum input clock
frequency of 1 MHz. If the selected input clock stops, pauses, or is gapped such that the 1 MHz minimum is not met for any
time interval, then the output clock(s) will be disabled (turned off). Once the paused input clock restarts, the output clock may
NOT start up immediately. Output start-up (turning back on) may be delayed for several input clock cycles until the internal
synchronizer determines the input clock is once again valid.
2. Click on the part number above to see a block diagram for each corresponding part number.
Table 1.2. Si5330x Ordering Guide
Part Number
Si53301-B-GM
1
Si53302-B-GM
1
Si53303-B-GM
1
Si53304-B-GM
1
Si53305-B-GM
1
Si53306-B-GM
1
Si53307-B-GM
1
Si53308-B-GM
1
Si53301/4-EVB
Package
32-QFN
44-QFN
44-QFN
32-QFN
44-QFN
16-QFN
16-QFN
32-QFN
Evaluation Board
Pb-Free, ROHS-6
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Temperature
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
–40 to 85 °C
—
Note:
1. Add an "R" at the end of the OPN to denote tape and reel ordering options.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 5, 2021
2
2
Table of Contents
1. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Universal, Any-Format Input Termination .
2.2 Internal Input Bias Resistors
2.3 Voltage Reference (V
REF
) .
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. 5
. 8
. 9
. 9
.10
.10
.10
.11
.11
.11
.12
.14
.15
.16
.18
.19
.19
2.4 Universal, Any-Format Output Buffer
2.6 Glitchless Clock Input Switching .
2.7 Synchronous Output Enable
2.9 Flexible Output Divider .
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2.8 Loss of Signal (LOS) Indicator .
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2.5 Input Mux (Si53301/02/04/05/07 Only) .
2.10 Power Supply (V
DD
and V
DDOX
) .
2.11 Output Clock Termination Options .
2.13 AC Timing Waveforms .
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.
2.12 LVCMOS Output Termination to Support 1.5 V and 1.2 V .
2.14 Typical Phase Noise Performance (Differential Input Clock)
2.16 Input Mux Noise Isolation .
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2.15 Typical Phase Noise Performance (Single-Ended Input Clock)
2.17 Power Supply Noise Rejection .
3. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .
4. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . .
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Si53301 Pin Descriptions
5.2 Si53302 Pin Descriptions
5.3 Si53303 Pin Descriptions
5.4 Si53304 Pin Descriptions
5.5 Si53305 Pin Descriptions
5.6 Si53306 Pin Descriptions
5.7 Si53307 Pin Descriptions
5.8 Si53308 Pin Descriptions
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20
29
36
.36
.39
.42
.45
.48
.52
.54
.56
6. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 16-QFN Package Diagram .
6.2 32-QFN Package Diagram .
6.3 44-QFN Package Diagram .
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59
.59
.60
.61
7. Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
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62
3
7.1 16-QFN Land Pattern.
7.2 32-QFN Land Pattern.
7.3 44-QFN Land Pattern.
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.62
.63
.64
8. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 Si53301/04/08 Top Markings .
8.2 Si53302/03/05 Top Markings .
8.3 Si53306/07 Top Markings .
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65
.65
.66
.67
9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
4
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 5, 2021
4
Si5330x Data Sheet • Functional Description
2. Functional Description
The Si5330x family of low-jitter, low-skew, universal/any-format buffers accepts most common differential or LVCMOS input signals.
These devices are available in multiple configurations customized for the end application (refer to
1. Ordering Guide
for more details on
configurations).
2.1 Universal, Any-Format Input Termination
The universal input stage enables simple interfacing to a wide variety of clock formats, including LVPECL, low-power LVPECL,
LVCMOS, LVDS, HCSL, and CML. The simplified tables below summarize the various ac- and dc-coupling options supported by the
device. For the best high-speed performance, the use of differential formats is recommended. For both single-ended and differential
input clocks, the fastest possible slew rate is recommended since low slew rates can increase the noise floor and degrade jitter
performance. Though not required, a minimum slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for
single-ended formats. See
AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance
for more information.
Table 2.1. AC-Coupled Clock Input Options
Clock Format
LVPECL/Low-power LVPECL
LVCMOS
LVDS
HCSL
CML
1.8 V
N/A
No
Yes
No
Yes
Table 2.2. DC-Coupled Clock Input Options
Clock Format
LVPECL/Low-power LVPECL
LVCMOS
LVDS
HCSL
CML
1.8 V
N/A
No
No
No
No
2.5/3.3 V
Yes
Yes
Yes
Yes
No
2.5/3.3 V
Yes
Yes
Yes
Yes
Yes
5
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 5, 2021
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