CP2201EK datasheet, PDF - EEWORLD Datasheet

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CP2201EK: DescriptionCP2200，CP2201 以太网传感器接口评估板; CategoryDevelopment board/suite/development tools Development board/development kit; File Size3MB，107 Pages; ManufacturerSilicon Labs; Websitehttps://www.silabs.com

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CP2201EK Overview

CP2200，CP2201 以太网传感器接口评估板

CP2201EK Parametric

Parameter Name	Attribute value
category
Maker	Silicon Labs
series	-
Package	Bulk
type	interface
Function	以太网传感器
Embedded	Yes, MCU, 8-bit
IC/parts used	CP2200，CP2201
Main attributes	温度和光传感器
What's included	board, cable, power supply
Auxiliary properties	GUI

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CP2200/1

INGLE

- C

H IP

T H E R N E T

ONTR OLLER

Ethernet Controller

IEEE 802.3 MAC and 10 BASE-T PHY



Fully compatible with 100/1000 BASE-T networks



Full/Half duplex with auto-negotiation



Automatic polarity detection and correction



Automatic retransmission on collision



Automatic padding and CRC generation



Supports broadcast and multi-cast MAC addressing



Integrated

Software Support

TCP/IP stack with device drivers



TCP/IP Stack Configuration Wizard



Hardware diagnostic software and example code



Royalty-free

Example Applications

sensing and monitoring



Inventory management



VoIP phone adapters



Point-of-sale devices



Network clocks



Embedded Web Server



Remote Ethernet-to-UART bridge



Remote

Parallel Host Interface (30 Mbps Transfer Rate)



8-bit

multiplexed or non-multiplexed mode



Only 11 I/O pins required in multiplexed mode

or Motorola

Bus Format



Interrupt on received packets and Wake-on-LAN



Intel

Supply Voltage



3.1

8 kB Flash Memory



8192

to 3.6 V

bytes ISP non-volatile memory



Factory pre-programmed unique 48-bit MAC Address



No external EEPROM required

Package

48-pin TQFP (9x9 mm footprint)



Pb-free 28-pin QFN (5x5 mm footprint)



Pb-free

Other Features

output drivers (Link/Activity)



Dedicated 2 kB RAM transmit buffer and 4 kB RAM

receive FIFO buffer



Power-on Reset



5 V Tolerant I/O



LED

Ordering Part Number



CP2200-GQ

(48-pin)



CP2201-GM (28-pin)

Temperature Range: –40 to +85 °C

20 MHz

XTAL

CP2200

8 kB

Flash

Clock

LED

Control

Parallel Bus

Host

Interface

2 kB

Tx Buffer

Ethernet

MAC

4 kB

Rx FIFO

Ethernet

PHY

ACT

LED

TX+/TX-

RJ-45

RX+/RX-

LINK

LED

Figure 1. Example System Diagram

Rev. 1.0 5/07

CP2200/1

CP2200/1

ABLE OF

ONTENTS

Section

Page

1. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2. Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

5. Pinout and Package Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.2. Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

6.3. Interrupt Request Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.4. Clocking Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.5. LED Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

6.6. Sending and Receiving Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7. Internal Memory and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1. Random Access to RAM Transmit and Receive Buffers . . . . . . . . . . . . . . . . . . . . . . 23

7.2. Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8. Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

9. Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9.1. Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

9.2. Power-fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.3. Oscillator-Fail Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.4. External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

9.5. Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.6. Determining the Source of the Last Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.7. De-Selecting Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10. Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

10.1. Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10.2. Link Detection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10.3. Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10.4. Shutdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10.5. Disabling Secondary Device Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

11. Transmit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

11.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

11.2. Transmitting a Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

11.3. Overriding Transmit Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

11.4. Transmit Buffer and AutoWrite Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

11.5. Transmit Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

12. Receive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

12.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

12.2. Reading a Packet Using the Autoread Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

12.3. Timing and Buffer Overflow Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

12.4. Initializing the Receive Buffer, Filter and Hash Table . . . . . . . . . . . . . . . . . . . . . . . 59

Rev. 1.0

CP2200/1

12.5. Receive Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

12.6. Advanced Receive Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

12.7. Receive Buffer Advanced Status and Control Registers . . . . . . . . . . . . . . . . . . . . .67

13. Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

13.1. Programming the Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

13.2. Reading the Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

13.3. Flash Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

14. Media Access Controller (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

14.1. Initializing the MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

14.2. Accessing the Indirect MAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

14.3. Indirect MAC Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

15. Physical Layer (PHY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

15.1. Auto-Negotiation and Duplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

15.2. Auto-Negotiation Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

15.3. Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

15.4. Link Integrity Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

15.5. Receiver Smart Squelch and Automatic Polarity Correction . . . . . . . . . . . . . . . . . . 89

15.6. Transmitter Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

15.7. Initializing the Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

16. Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

16.1. Non-Multiplexed Intel Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

16.2. Multiplexed Intel Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

16.3. Non-Multiplexed Motorola Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

16.4. Multiplexed Motorola Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

17. Revision-Specific Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

17.1. Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

17.2. MAC Address Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Rev. 1.0

CP2200/1

1. System Overview

The CP2200/1 is a single-chip Ethernet controller containing an integrated IEEE 802.3 Ethernet Media Access

Controller (MAC), 10BASE-T Physical Layer (PHY), and 8 kB Non-Volatile Flash Memory available in a compact

5 x 5 mm QFN-28 package (sometimes called “MLF” or “MLP”) and a 48-pin TQFP package. The CP2200/1 can

add Ethernet connectivity to any microcontroller or host processor with 11 or more Port I/O pins. The 8-bit parallel

interface bus supports both Intel and Motorola bus formats in multiplexed and non-multiplexed mode. The data

transfer rate in non-multiplexed mode can exceed 30 Mbps.

The on-chip Flash memory may be used to store user constants, web server content, or as general purpose non-

volatile memory. The Flash is factory preprogrammed with a unique 48-bit MAC address stored in the last six

memory locations. Having a unique MAC address stored in the CP2200/1 often removes the serialization step from

the product manufacturing process of most embedded systems.

The CP2200/1 has four power modes with varying levels of functionality that allow the host processor to manage

the overall system power consumption. The optional interrupt pin also allows the host to enter a “sleep” mode and

awaken when a packet is received or when the CP2200/1 is plugged into a network. Auto-negotiation allows the

device to automatically detect the most efficient duplex mode (half/full duplex) supported by the network.

The Ethernet Development Kit (Ethernet-DK) bundles a C8051F120 MCU Target Board, CP2200 Ethernet

Development Board (AB4), the Silicon Laboratories IDE, all necessary debug hardware, and a TCP/IP

Configuration Wizard. The Ethernet Development Kit includes all hardware, software, and examples necessary to

design an embedded system using the CP2200. The CP2200 Ethernet Development Board is also compatible with

the C8051F020TB and C8051F340TB. Individual target boards may be purchased online by visiting

www.silabs.com.

Rev. 1.0

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