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IS62WV25616CLL-55B2I

Description
Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, MINI, BGA-48
Categorystorage    storage   
File Size88KB,13 Pages
ManufacturerIntegrated Silicon Solution ( ISSI )
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IS62WV25616CLL-55B2I Overview

Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, MINI, BGA-48

IS62WV25616CLL-55B2I Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIntegrated Silicon Solution ( ISSI )
Parts packaging codeBGA
package instructionLFBGA,
Contacts48
Reach Compliance Codenot_compliant
ECCN code3A991.B.2.A
Maximum access time55 ns
JESD-30 codeR-PBGA-B48
JESD-609 codee0
length8 mm
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width16
Number of functions1
Number of terminals48
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize256KX16
Package body materialPLASTIC/EPOXY
encapsulated codeLFBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.35 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.5 V
Nominal supply voltage (Vsup)3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch0.75 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width6 mm
Base Number Matches1
IS62WV25616CLL
256K x 16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC SRAM
FEATURES
• High-speed access time: 55ns, 70ns
• CMOS low power operation
– 1.5 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply
– 2.5V--3.6V V
DD
(62WV25616CLL)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• 2CS Option Available
ISSI
MARCH 2003
®
DESCRIPTION
The
ISSI
IS62WV25616CLL are high-speed, low power, 4M
bit SRAMs organized as 256K words by 16 bits. It is
fabricated using
ISSI
's high-performance CMOS technology.
This highly reliable process coupled with innovative circuit
design techniques, yields high-performance and low power
consumption devices.
When
CS1
is HIGH (deselected) or when CS2 is LOW
(deselected) or when
CS1
is LOW, CS2 is HIGH and both
LB
and
UB
are HIGH, the device assumes a standby mode
at which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE)
controls both writing and reading of the memory. A
data byte allows Upper Byte
(UB)
and Lower Byte (LB)
access.
The IS62WV25616CLL are packaged in the JEDEC standard
48-pin mini BGA (6mm x 8mm). 48-pin mini BGA is
available both in 1CS and 2CS options.
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16
MEMORY ARRAY
V
DD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CS2
CS1
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
03/13/03
1

IS62WV25616CLL-55B2I Related Products

IS62WV25616CLL-55B2I IS62WV25616CLL-55B2 IS62WV25616CLL-70B2I IS62WV25616CLL-70BI
Description Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, MINI, BGA-48 Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, MINI, BGA-48 Standard SRAM, 256KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, MINI, BGA-48 Standard SRAM, 256KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, MINI, BGA-48
Is it Rohs certified? incompatible incompatible incompatible incompatible
Maker Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI ) Integrated Silicon Solution ( ISSI )
Parts packaging code BGA BGA BGA BGA
package instruction LFBGA, LFBGA, 6 X 8 MM, MINI, BGA-48 6 X 8 MM, MINI, BGA-48
Contacts 48 48 48 48
Reach Compliance Code not_compliant not_compliant unknown unknown
ECCN code 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A
Maximum access time 55 ns 55 ns 70 ns 70 ns
JESD-30 code R-PBGA-B48 R-PBGA-B48 R-PBGA-B48 R-PBGA-B48
JESD-609 code e0 e0 e0 e0
length 8 mm 8 mm 8 mm 8 mm
memory density 4194304 bit 4194304 bit 4194304 bit 4194304 bit
Memory IC Type STANDARD SRAM STANDARD SRAM STANDARD SRAM STANDARD SRAM
memory width 16 16 16 16
Number of functions 1 1 1 1
Number of terminals 48 48 48 48
word count 262144 words 262144 words 262144 words 262144 words
character code 256000 256000 256000 256000
Operating mode ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS
Maximum operating temperature 85 °C 70 °C 85 °C 85 °C
Minimum operating temperature -40 °C - -40 °C -40 °C
organize 256KX16 256KX16 256KX16 256KX16
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code LFBGA LFBGA LFBGA LFBGA
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form GRID ARRAY, LOW PROFILE, FINE PITCH GRID ARRAY, LOW PROFILE, FINE PITCH GRID ARRAY, LOW PROFILE, FINE PITCH GRID ARRAY, LOW PROFILE, FINE PITCH
Parallel/Serial PARALLEL PARALLEL PARALLEL PARALLEL
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 1.35 mm 1.35 mm 1.35 mm 1.35 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 2.5 V 2.5 V 2.5 V 2.5 V
Nominal supply voltage (Vsup) 3 V 3 V 3 V 3 V
surface mount YES YES YES YES
technology CMOS CMOS CMOS CMOS
Temperature level INDUSTRIAL COMMERCIAL INDUSTRIAL INDUSTRIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form BALL BALL BALL BALL
Terminal pitch 0.75 mm 0.75 mm 0.75 mm 0.75 mm
Terminal location BOTTOM BOTTOM BOTTOM BOTTOM
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 6 mm 6 mm 6 mm 6 mm
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