5962R9562101V9A datasheet, PDF

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5962R9562101V9A: Description4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, UUC16, DIE-16; Categorylogic logic; File Size139KB，24 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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5962R9562101V9A Overview

4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, UUC16, DIE-16

5962R9562101V9A Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	incompatible
Parts packaging code	DIE
package instruction	DIE, DIE OR CHIP
Contacts	16
Reach Compliance Code	compliant
Counting direction	BIDIRECTIONAL
series	4000/14000/40000
JESD-30 code	R-XUUC-N16
JESD-609 code	e0
Load capacitance (CL)	50 pF
Load/preset input	YES
Logic integrated circuit type	BINARY COUNTER
Operating mode	SYNCHRONOUS
Number of digits	4
Number of functions	1
Number of terminals	16
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	UNSPECIFIED
encapsulated code	DIE
Encapsulate equivalent code	DIE OR CHIP
Package shape	RECTANGULAR
Package form	UNCASED CHIP
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5/15 V
Prop。Delay @ Nom-Sup	675 ns
propagation delay (tpd)	500 ns
Certification status	Not Qualified
Filter level	MIL-PRF-38535 Class V
Maximum supply voltage (Vsup)	18 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	NO LEAD
Terminal location	UPPER
Maximum time at peak reflow temperature	NOT SPECIFIED
total dose	100k Rad(Si) V
Trigger type	POSITIVE EDGE
minfmax	5.5 MHz
Base Number Matches	1

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REVISIONS

LTR

DESCRIPTION

Changes in accordance with NOR 5962-R164-97.

DATE (YR-MO-DA)

97-02-24

APPROVED

Monica L. Poelking

Changes in accordance with NOR 5962-R377-97.

97-07-24

Raymond Monnin

Incorporate revisions A and B. Update boilerplate to MIL-PRF-38535

requirements. Editorial changes throughout. – LTG

03-09-12

Thomas M. Hess

REV

SHEET

REV

SHEET

REV STATUS

OF SHEETS

PMIC N/A

REV

SHEET

PREPARED BY

Joseph A. Kerby

STANDARD

MICROCIRCUIT

DRAWING

THIS DRAWING IS AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

CHECKED BY

Monica L. Poelking

APPROVED BY

Monica L. Poelking

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216

http://www.dscc.dla.mil

DRAWING APPROVAL DATE

96-01-29

MICROCIRCUIT, DIGITAL, RADIATION

HARDENED CMOS, PRESETTABLE UP/DOWN

COUNTER, MONOLITHIC SILICON

AMSC N/A

REVISION LEVEL

SIZE

CAGE CODE

SHEET

67268

1 OF

5962-95621

DSCC FORM 2233

APR 97

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

5962-E542-03

1.3 Absolute maximum ratings. 1/ 2/ 3/

Supply voltage range (V

) ........................................................................................ -0.5 V dc to +20 V dc

Input voltage range ................................................................................................... -0.5 V dc to V

+ 0.5 V dc

DC input current, any one input .................................................................................

±10

Device dissipation per output transistor ..................................................................... 100 mW

Storage temperature range (T

STG

).............................................................................. -65°C to +150°C

Lead temperature (soldering, 10 seconds) ................................................................ +265°C

Thermal resistance, junction-to-case (θ

Case E .................................................................................................................... 24°C/W

Case X .................................................................................................................... 29°C/W

Thermal resistance, junction-to-ambient (θ

Case E .................................................................................................................... 73°C/W

Case X .................................................................................................................... 114°C/W

Junction temperature (T

)........................................................................................... +175°C

Maximum power dissipation at T

= +125°C (P

): 4/

Case E .................................................................................................................... 0.68 W

Case X .................................................................................................................... 0.44 W

1.4 Recommended operating conditions.

Supply voltage range (V

) ........................................................................................

Case operating temperature range (T

) .....................................................................

Input voltage (V

) ......................................................................................................

Output voltage (V

OUT

) .................................................................................................

Radiation features:

Total dose .............................................................................................................

Single event phenomenon (SEP) effective

linear energy threshold, no upsets or latchup (see 4.4.4.5) ................................

Dose rate upset (20 ns pulse) ...............................................................................

Dose rate latch-up ................................................................................................

Dose rate survivability ..........................................................................................

Neutron irradiated ................................................................................................

2. APPLICABLE DOCUMENTS

2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a

part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in

the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the

solicitation.

SPECIFICATION

DEPARTMENT OF DEFENSE

MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.

3.0 V dc to +18 V dc

-55°C to +125°C

0 V to V

1 x 10 Rads (Si)

>75 MeV/(cm /mg) 5/

> 5 x 10 Rads(Si)/s 5/

> 2 x 10 Rads(Si)/s 5/

> 5 x 10 Rads(Si)/s 5/

> 1 x 10 neutrons/cm 6/

Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the

maximum levels may degrade performance and affect reliability.

Unless otherwise specified, all voltages are referenced to V

The limits for the parameters specified herein shall apply over the full specified V

range and case temperature range of

-55°C to +125°C unless otherwise noted.

If device power exceeds package dissipation capability, provide heat sinking or derate linearly (the derating is

based on

) at the following rate:

Case E ....................................................................................................................... 13.7 mW/°C

Case X ....................................................................................................................... 8.8 mW/°C

Guaranteed by design or process but not tested.

Device type 02 only.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216-5000

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-95621

SHEET

STANDARDS

DEPARTMENT OF DEFENSE

MIL-STD-883 -

MIL-STD-1835 -

HANDBOOKS

DEPARTMENT OF DEFENSE

MIL-HDBK-103 -

MIL-HDBK-780 -

List of Standard Microcircuit Drawings.

Standard Microcircuit Drawings.

Test Method Standard Microcircuits.

Interface Standard Electronic Component Case Outlines.

(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization

Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text

of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with

MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The

modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for

device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified

herein.

3.1.1 Microcircuit die. For the requirements for microcircuit die, see appendix A to this document.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified

in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.

3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.

3.2.3 Truth table. The truth table shall be as specified on figure 2.

3.2.4 Radiation test connections. The radiation test connections shall be as specified in table III herein.

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full

case operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical

tests for each subgroup are defined in table I.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space

limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the

RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.

Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A.

3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in

MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.

STANDARD

MICROCIRCUIT DRAWING

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43216-5000

DSCC FORM 2234

APR 97

SIZE

REVISION LEVEL

5962-95621

SHEET

5962R9562101V9A Related Products

	5962R9562101V9A	5962R9562102V9A	5962R9562101VXC	5962R9562102VXC	5962R9562101VEC	5962R9562102VEC
Description	4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, UUC16, DIE-16	4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, UUC16, DIE-16	4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, CDFP16, CERAMIC, DFP-16	4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, CDFP16, CERAMIC, FP-16	4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, CDIP16, CERAMIC, DIP-16	4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, CDIP16, CERAMIC, DIP-16
Parts packaging code	DIE	DIE	DFP	DFP	DIP	DIP
package instruction	DIE, DIE OR CHIP	DIE, DIE OR CHIP	DFP, FL16,.3	DFP, FL16,.3	DIP, DIP16,.3	DIP, DIP16,.3
Contacts	16	16	16	16	16	16
Reach Compliance Code	compliant	compliant	compliant	unknown	compliant	compliant
Counting direction	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL	BIDIRECTIONAL
series	4000/14000/40000	4000/14000/40000	4000/14000/40000	4000/14000/40000	4000/14000/40000	4000/14000/40000
JESD-30 code	R-XUUC-N16	R-XUUC-N16	R-CDFP-F16	R-CDFP-F16	R-CDIP-T16	R-CDIP-T16
JESD-609 code	e0	e0	e4	e4	e4	e4
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
Load/preset input	YES	YES	YES	YES	YES	YES
Logic integrated circuit type	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER	BINARY COUNTER
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Number of digits	4	4	4	4	4	4
Number of functions	1	1	1	1	1	1
Number of terminals	16	16	16	16	16	16
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C
Package body material	UNSPECIFIED	UNSPECIFIED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIE	DIE	DFP	DFP	DIP	DIP
Encapsulate equivalent code	DIE OR CHIP	DIE OR CHIP	FL16,.3	FL16,.3	DIP16,.3	DIP16,.3
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	UNCASED CHIP	UNCASED CHIP	FLATPACK	FLATPACK	IN-LINE	IN-LINE
power supply	5/15 V	5/15 V	5/15 V	5/15 V	5/15 V	5/15 V
Prop。Delay @ Nom-Sup	675 ns	675 ns	675 ns	675 ns	675 ns	675 ns
propagation delay (tpd)	500 ns	500 ns	675 ns	675 ns	675 ns	675 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Filter level	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V	MIL-PRF-38535 Class V
Maximum supply voltage (Vsup)	18 V	18 V	18 V	18 V	18 V	18 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY
Terminal surface	TIN LEAD	TIN LEAD	GOLD	GOLD	GOLD	GOLD
Terminal form	NO LEAD	NO LEAD	FLAT	FLAT	THROUGH-HOLE	THROUGH-HOLE
Terminal location	UPPER	UPPER	DUAL	DUAL	DUAL	DUAL
total dose	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V	100k Rad(Si) V
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
minfmax	5.5 MHz	5.5 MHz	1.48 MHz	5.5 MHz	1.48 MHz	5.5 MHz
Base Number Matches	1	1	1	1	1	1
MaximumI(ol)	-	-	0.00064 A	0.00064 A	0.00064 A	0.00064 A
Terminal pitch	-	-	1.27 mm	1.27 mm	2.54 mm	2.54 mm

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