Data Sheet
FEATURES
Input voltage range: 2.7 V to 5.5 V
600 mA maximum load current
95% efficiency
Low duty cycle operation
Only 3 tiny external ceramic components
3 MHz typical operating frequency
Fixed output voltage of 1.2 V or 1.375 V
Adjustable output voltage up to 3.3 V
0.01 µA shutdown supply current
Automatic power save mode
Internal synchronous rectifier
Internal soft start
Internal compensation
Enable/shutdown logic input
Undervoltage lockout
Current limit protection
Thermal shutdown
Small 8-lead, 3 mm × 3 mm LFCSP
Low Duty Cycle, 600 mA, 3 MHz, Synchronous
Step-Down DC-to-DC Converter
ADP2102
TYPICAL APPLICATION CIRCUIT
INPUT VOLTAGE
2.7V TO 5.5V
C
IN
2.2µF
V
IN
LX
OUTPUT VOLTAGE
1.2V OR 1.375V
C
OUT
2.2µF
L
1µH
ADP2102
FORCED
CCM
MODE
EN
DCM/
CCM
OFF
FB/OUT
GND
ON
Figure 1.
APPLICATIONS
USB powered devices
WLAN and gateways
Point of loads
Processor core power from 5 V
Digital cameras
PDAs and palmtop computers
Portable media players, GPS
The
ADP2102
is available in both fixed and adjustable output
voltage options with a 600 mA maximum output current. The fixed
output voltage options are 1.2 V and 1.375 V. The adjustable output
voltage options are available from 1.5 V to 3.3 V. The
ADP2102
requires only three external components and consumes 0.01 µA
in shutdown mode.
The
ADP2102
is available in an 8-lead LFCSP and is specified
for the −40°C to +85°C temperature range.
100
V
IN
= 2.7V
95
V
IN
= 3V
90
V
OUT
= 1.375V
T
A
= 25°C
EFFICIENCY (%)
GENERAL DESCRIPTION
The
ADP2102
is a synchronous step-down dc-to-dc converter
that converts a 2.7 V to 5.5 V unregulated input voltage to a lower
regulated output voltage with up to 95% efficiency and 1%
accuracy. The low duty cycle capability of the
ADP2102
is ideal for
USB applications or 5 V systems that power up submicron subvolt
processor cores. Its 3 MHz typical operating frequency and excel-
lent transient response allow the use of small, low cost 1 µH
inductors and 2.2 µF ceramic capacitors. At medium-to-high
load currents, it uses a current mode, pseudofixed frequency pulse-
width modulation to extend battery life. To ensure the longest
battery life in portable applications, the
ADP2102
has a power save
mode (PSM) that reduces the switching frequency under light
load conditions to significantly reduce quiescent current.
85
V
IN
= 3.6V
80
75
70
65
V
IN
= 4.2V
100
LOAD CURRENT (mA)
1000
Figure 2. Efficiency vs. Load Current at V
OUT
= 1.375 V
Rev. C
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license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
06631-052
60
10
06631-001
ADP2102
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Typical Application Circuit ............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
Boundary Condition .................................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 13
Control Scheme .......................................................................... 13
Constant On-Time Timer ......................................................... 13
Forced Continuous Conduction Mode ................................... 13
Power Save Mode ........................................................................ 13
Synchronous Rectification ........................................................ 14
Current Limit .............................................................................. 14
Data Sheet
Soft Start ...................................................................................... 15
Enable........................................................................................... 15
Undervoltage Lockout ............................................................... 15
Thermal Shutdown .................................................................... 15
Applications Information .............................................................. 16
Inductor Selection ...................................................................... 16
Input Capacitor Selection .......................................................... 16
Output Capacitor Selection....................................................... 16
Typical Application Circuits ..................................................... 17
Setting the Output Voltage ........................................................ 19
Efficiency Considerations ......................................................... 19
Thermal Considerations............................................................ 20
Design Example .......................................................................... 20
Circuit Board Layout Recommendations ................................... 22
Recommended Layout ............................................................... 22
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
7/2016—Rev. B to Rev. C
Changed ADP2102-ADJ to ADP2102 Adjustable Output
Voltage Options, ADP2102-FXD to ADP2102 Fixed Output
Voltage Options, ADP2102-xx to ADP2102 Fixed Output
Voltage Options, and CP-8-2 to CP-8-13 ................... Throughout
Moved Figure 1; Renumbered Sequentially .................................. 1
Changes to Features Section, General Description Section, and
Figure 1 .............................................................................................. 1
Added Figure 2 Caption................................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Figure 3 and Table 4 ..................................................... 5
Changes to Figure 47 and Figure 48............................................. 17
Changes to Figure 49 and Figure 50............................................. 18
Changes to Table 7 .......................................................................... 19
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
9/2007—Rev. A to Rev. B
Changes to Features Section, Applications Section, and General
Description Section ...........................................................................1
Changes to Table 4.............................................................................5
Changes to Table 6.......................................................................... 17
Changes to Table 7.......................................................................... 19
Changes to Circuit Board Layout Recommendations Section ...... 21
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
6/2007—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 23
6/2007—Revision 0: Initial Version
Rev. C | Page 2 of 24
Data Sheet
SPECIFICATIONS
V
IN
= 3.6 V, EN = V
IN
, MODE = V
IN
, T
A
= 25°C, unless otherwise noted.
Bold values
indicate −40°C ≤ T
A
≤ +85°C.
1
Table 1.
Parameter
INPUT CHARACTERISTICS
Input Voltage Range
2
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
OUTPUT CHARACTERISTICS
Output Voltage Range
Output Voltage Range
Output Voltage Initial Accuracy
Test Conditions/Comments
Min
2.7
2.2
Typ
ADP2102
Max
5.5
2.5
Unit
V
V
mV
V
V
%
%
%
%
V
IN
rising
2.4
220
Load Regulation
Line Regulation
FEEDBACK CHARACTERISTICS
FB Regulation Voltage
FB Bias Current
FB Impedance
CURRENT CHARACTERISTICS
Operating Current
Shutdown Current
Output Current
LX (SWITCH NODE) CHARACTERISTICS
LX On Resistance
LX Leakage Current
LX Minimum Off Time
LX On Time
ADP2102
fixed output voltage options
ADP2102
adjustable output voltage options
ADP2102
fixed output voltage options, T
A
= 25°C, I
LOAD
= 0 mA
ADP2102
fixed output voltage options, −40°C ≤T
A
≤ 85°C,
I
LOAD
= 0 mA
V
OUT
= 1.2 V to 1.375 V, I
LOAD
= 0 mA to 600 mA
V
IN
= 2.7 V to 5.5 V, I
LOAD
= 10 mA
ADP2102
adjustable output voltage options
ADP2102
adjustable output voltage options
ADP2102
fixed output voltage options
ADP2102
PSM mode, I
LOAD
= 0 mA
EN = 0 V
ADP2102,
V
IN
= 2.7 V to 5.5 V
P-channel switch, I
LX
= 100 mA
N-channel synchronous rectifier, I
LX
= 100 mA
V
IN
= 5.5 V, V
LX
= 0 V, 5.5 V
ADP2102
fixed output voltage options,
ADP2102
adjustable output
voltage options
1.2 V fixed output voltage
1.375 V fixed output voltage
ADP2102-3,
V
OUT
= 1.5 V
ADP2102-3,
V
OUT
= 1.875 V
ADP2102-4,
V
OUT
= 3.3 V (V
IN
= 5 V)
1.2
1.5
−1
−2
0.5
0.3
784
800
375
70
0.01
1.375
3.3
+1
+2
816
50
mV
nA
kΩ
μA
μA
mA
mΩ
mΩ
μA
ns
ns
ns
ns
ns
ns
A
V
V
μA
μs
°C
°C
99
1
600
600
400
1
325
200
100
100
135
155
200
198
131
165
177
226
238
1
160
195
210
275
270
Valley Current Limit
ENABLE, MODE CHARACTERISTICS
EN, MODE Input High Threshold
EN, MODE Input Low Threshold
EN, MODE Input Leakage Current
SOFT START PERIOD
THERMAL CHARACTERISTICS
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
1
2
1.3
V
IN
= 5.5 V, EN = MODE = 0 V, 5.5 V
250
500
150
15
0.4
1
800
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
The input voltage (V
IN
) range over which the rest of the specifications are valid. The device operates as expected until V
IN
goes below the UVLO threshold.
Rev. C | Page 3 of 24
ADP2102
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
AVIN, EN, MODE, FB/OUT to AGND
LX to PGND
PVIN to PGND
PGND to AGND
AVIN to PVIN
Operating Ambient Temperature Range
Junction Temperature Range
Storage Temperature Range
Soldering Conditions
1
Data Sheet
THERMAL RESISTANCE
Rating
−0.3 V to +6 V
−0.3 V to (V
IN
+ 0.3 V)
−0.3 V to +6 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−40°C to +85°C
1
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
The
ADP2102
can be damaged when junction temperature limits are exceeded.
Monitoring ambient temperature does not guarantee that TJ is within the
specified temperature limits. In applications where high power dissipation
and poor thermal resistance are present, the maximum ambient temperature
may have to be derated. In applications with moderate power dissipation
and low PCB thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature is within
specification limits. The junction temperature (T
J
) of the device is dependent
on the ambient temperature (T
A
), the power dissipation of the device (PD),
and the junction-to-ambient thermal resistance of the package (θ
JA
). Maximum
junction temperature (T
J
) is calculated from the ambient temperature (T
A
)
and power dissipation (PD) using the formula
T
J
=
T
A
+ (θ
JA
×
PD).
Unless
otherwise specified, all other voltages are referenced to AGND.
Junction-to-ambient thermal resistance (θ
JA
) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, attention to thermal board
design is required. The value of θ
JA
may vary, depending on PCB
material, layout, and environmental conditions. Specified value
of θ
JA
is based on a 4-layer, 4 in × 3 in, 2 1/2 oz copper board,
as per JEDEC standards. For more information, see the
AN-772
Application Note,
A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP).
Table 3. Thermal Resistance
Package Type
8-Lead LFCSP
Maximum Power Dissipation
θ
JA
54
0.74
Unit
°C/W
W
BOUNDARY CONDITION
Natural convection, 4-layer board, exposed pad soldered to PCB.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. C | Page 4 of 24
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
MODE 1
EN 2
FB/OUT 3
AGND 4
8 AVIN
ADP2102
ADP102
TOP VIEW
(Not to Scale)
7 PVIN
6 LX
5 PGND
06631-003
NOTES
1. CONNECT THE EXPOSED PAD TO THE GROUND PLANE.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
MODE
EN
FB/OUT
Description
Mode Input. To set the
ADP2102
to forced continuous conduction mode (CCM), drive MODE high. To set the
ADP2102
to power save mode/auto mode (PSM), drive MODE low.
Enable Input. Drive EN high to turn on the
ADP2102.
Drive EN low to turn it off and reduce the input current to
0.1 µA. This pin cannot be left floating.
Output Sense Input or Feedback Input. For the fixed output voltage versions, OUT is the top of the internal resistive
voltage divider. Connect OUT to the output voltage. For the adjustable output voltage versions (no suffix), FB is the
input to the error amplifier. Drive FB through a resistive voltage divider to set the output voltage. The FB regulation
threshold is 0.8 V.
Analog Ground. Connect AGND to PGND at a single point as close to the
ADP2102
as possible. The exposed pad is
electrically common with the analog ground pin.
Power Ground.
Switch Output. LX is the drain of the P-channel MOSFET switch and the N-channel synchronous rectifier. Connect
the output LC filter between LX and the output voltage.
Power Source Input. Drive PVIN with a 2.7 V to 5.5 V power source. A ceramic bypass capacitor of 2.2 µF or greater is
required on this pin to the nearest PGND plane.
Power Source Input. AVIN is the supply for the
ADP2102
internal circuitry. This pin can be connected in three
different ways.
For noise reduction, place an external RC filter between PVIN and AVIN. The recommended values for the external
RC filter are 10 Ω and 0.1 µF, respectively. This configuration can be used for all loads.
For light-to-medium loads up to 300 mA, the AVIN pin and the PVIN pin can be shorted together.
For light-to-heavy loads (greater than 300 mA), bypass the AVIN pin with a 1 pF to 0.01 µF capacitor to the nearest
PGND plane. Do not short the AVIN and PVIN pins when using only a bypass capacitor.
Exposed Pad. Connect the exposed pad to the ground plane.
4
5
6
7
8
AGND
PGND
LX
PVIN
AVIN
0
EPAD
Rev. C | Page 5 of 24
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