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LTC2223IUK#TRPBF

Description
12 位模数转换器 1 输入 1 管线 48-QFN(7x7)
Categorysemiconductor    ADC/DAC - professional data collection   
File Size916KB,28 Pages
ManufacturerADI
Websitehttps://www.analog.com
Environmental Compliance
Download Datasheet Parametric View All

LTC2223IUK#TRPBF Overview

12 位模数转换器 1 输入 1 管线 48-QFN(7x7)

LTC2223IUK#TRPBF Parametric

Parameter NameAttribute value
category
MakerADI
series-
PackageTape and Reel (TR)
Number of digits12
Sample rate (per second)80M
Number of inputs1
input typeDifferential, single-ended
Data interfaceLVDS - parallel, parallel
ConfigurationS/H-ADC
Ratio - S/H:ADC1:1
Architecturepipeline
Reference typeoutside, inside
Voltage - Power Supply, Analog3.1V ~ 3.5V
Voltage - Power Supply, Digital3.1V ~ 3.5V
characteristic-
Operating temperature-40°C ~ 85°C
Package/casing48-WFQFN Exposed Pad
Supplier device packaging48-QFN(7x7)
Installation typesurface mount type
Number of A/D converters1
Basic product numberLTC2223
LTC2222/LTC2223
12-Bit,105Msps/
80Msps ADCs
FEATURES
n
n
n
n
n
n
n
n
n
n
n
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DESCRIPTION
The LTC
®
2222 and LTC2223 are 105Msps/80Msps, sam-
pling 12-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. The LTC2222/
LTC2223 are perfect for demanding communications
applications with AC performance that includes 68dB
SNR and 80dB spurious free dynamic range for signals
up to 170MHz. Ultralow jitter of 0.15ps
RMS
allows
undersampling of IF frequencies with excellent noise
performance.
DC specs include ±0.3LSB INL (typ), ±0.2LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.5LSB
RMS
.
A separate output power supply allows the outputs to
drive 0.5V to 3.6V logic.
The ENC
+
and ENC
inputs may be driven differentially
or single ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n
Sample Rate: 105Msps/80Msps
68dB SNR up to 140MHz Input
80dB SFDR up to 170MHz Input
775MHz Full Power Bandwidth S/H
Single 3.3V Supply
Low Power Dissipation: 475mW/366mW
Selectable Input Ranges: ±0.5V or ±1V
No Missing Codes
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)
80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)
48-Pin QFN Package
APPLICATIONS
n
n
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Wireless and Wired Broadband Communication
Cable Head-End Systems
Power Amplifier Linearization
Communications Test Equipment
TYPICAL APPLICATION
V
DD
3.3V
100
REFH
REFL
FLEXIBLE
REFERENCE
0V
DD
0.5V TO 3.6V
95
90
SFDR (dBFS)
85
80
2nd or 3rd
75
70
65
CLOCK/DUTY
CYCLE
CONTROL
22223 TA01
SFDR vs Input Frequency
4th OR HIGHER
+
ANALOG
INPUT
INPUT
S/H
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
OUTPUT
DRIVERS
D11
D0
0GND
60
0
100
200
300
400
500
INPUT FREQUENCY (MHz)
600
22223 TA01b
ENCODE
INPUT
22223fb
1
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