PRELIMINARY
DS89C420
Ultra High Speed Microcontroller
www.dalsemi.com
FEATURES
80C52 compatible
−
8051 pin and instruction set compatible
−
Four bidirectional I/O ports
−
Three 16 bit timer counters
−
256 bytes scratchpad RAM
On-chip memory
−
16k Flash memory
−
In-Application programmable
−
In System programmable via serial port
−
1k SRAM for MOVX
ROMSIZE feature
−
Selects internal program memory size from 0
to16k
−
Allows access to entire external memory
map
−
Dynamically adjustable by software
High Speed Architecture
−
One clock per machine cycle
−
DC to 50 MHz operation
−
Single cycle instruction in 20 ns
−
Optional variable length MOVX to access
fast/slow peripherals
−
Dual data pointers with Auto
Increment/Decrement and Toggle Select
−
Supports four paged modes
Power Management Mode
−
Programmable clock divider
−
Automatic hardware and software exit
Two full duplex serial ports
Programmable Watchdog timer
Thirteen interrupt sources (six external)
Five levels of interrupt priority
Power Fail Reset
Early Warning Power Fail Interrupt
PIN ASSIGNMENT
P1.0/T2
P1.1/T2EX
P1.2/RXD1
P1.3/TXD1
P1.4/INT2
P1.5/INT3
P1.6/INT4
P1.7/INT5
RST
P3.0/RXD0
P3.1/TXD0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
V
SS
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10 DALLAS 31
11 DS89C420 30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
VCC
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
EA/V
PP
ALE/PROG
PSEN
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
40-Pin DIP
6
7
1
40
39
DALLAS
DS89C420
17
18
28
29
44-Pin PLCC
33
23
34
DALLAS
DS89C420
22
44
12
1
11
44-Pin TQFP
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092200
DS89C420
DESCRIPTION
The DS89C420 offers the highest performance available in 8051-compatible microcontrollers. It features a
redesigned processor core which executes every 8051 instruction up to 12 times faster than the original for
the same crystal speed, thus allowing very significant improvements using the same code and crystal. The
DS89C420 offers a maximum crystal speed of 50 MHz, achieving execution rates up to 50 MIPs for short
instructions.
The DS89C420 is pin-compatible with all three packages of the standard 8051 and includes standard
resources such as three timer/counters, serial port, and four 8-bit I/O ports. It features 16 kbits of “In System
Programmable” flash memory which can be programmed
in system
from an I/O port using a built in program
memory loader or from resident user software. It can also be loaded externally using standard commercially
available programmers.
Besides greater speed, the DS89C420 includes 1 kbits of data RAM, a second full hardware serial port, seven
additional interrupts, two more levels of interrupt priority, programmable Watchdog timer, Brown-out
Monitor, and Power-Fail Reset. The device also provides dual data pointers (DPTRs) to speed-up block data
memory moves and this feature is further enhanced with a new selectable Automatic Increment/Decrement
and Toggle Select operation . The speed of MOVX data memory access can be adjusted by adding stretch
values up to ten machine cycle times for flexibility in selecting external memory and peripherals.
A Power Management Mode (PMM) uses significantly lower power consumption by slowing the CPU
execution rate from 1 clock period per cycle to 1024 clock periods per cycle. A selectable switchback feature
can automatically cancel this mode to enable a normal speed response to interrupts.
The EMI reduction feature disables the ALE signal when the processor is not accessing external memory.
ORDERING INFORMATION:
PART NUMBER
DS89C420 - MCS
DS89C420 - QCS
DS89C420 - ECS
DS89C420 - MNS
DS89C420 - QNS
DS89C420 - ENS
PACKAGE
40-pin plastic DIP
44-pin PLCC
44-pin TQFP
40-pin plastic DIP
44-pin PLCC
44-pin TQFP
MAX.
CLOCK SPEED
50 MHz
50 MHz
50 MHz
50 MHz
50 MHz
50 MHz
TEMPERATURE
RANGE
0
O
C to+70
O
C
0
O
C to+70
O
C
0
O
C to+70
O
C
-40
O
C to +85
O
C
-40
O
C to +85
O
C
-40
O
C to +85
O
C
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DS89C420
DS89C420 BLOCK DIAGRAM
Figure 1
Control &
Sequencer
Interrupt
SFRs
PC
AR Inc
AR
Internal
Registers
CPU
DPTR
DPTR1
SP
Decoder
IR
Internal Control Bus
Address Bus
Serial I/O
Timer/
Counters
1Kx 8
RAM
16K x 8
Flash
I/O Ports
Watchdog Timer
&
Power Manager
Clock &
Reset
Memory
Control
ROM
Loader
ALE/PROG
XTAL1
XTAL2
RST
PSEN
EA
P0 P1 P2 P3
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DS89C420
PIN DESCRIPTION
Table 1
DIP
40
20
9
PLCC
12, 44
1 , 22,
23, 34
10
TQFP
6, 38
16, 17,
28, 39
4
SIGNAL
NAME
V
CC
GND
RST
V
CC
- +5V
GND
– Logic Ground.
External Reset.
The RST input pin is bi-directional and
contains a Schmitt Trigger to recognize external active high
Reset inputs. The pin also employs an internal pulldown resistor
to allow for a combination of wire OR’d external reset sources.
An RC is not required for power-up, as the device provides this
function internally.
XTAL1, XTAL2
- The crystal oscillator pins XTAL1 and
XTAL2 provide support for fundamental mode parallel resonant,
AT cut crystals. XTAL1 also acts as an input if there is an
external clock source in place of a crystal. XTAL2 serves as the
output of the crystal amplifier.
Program Store Enable output.
This signal is commonly
connected to optional external program memory memory as a
chip enable.
PSEN
provides an active low pulse and is driven
high when external program memory is not being accessed.
Address Latch Enable
Functions as a clock to latch the
external address LSB from the multiplexed address/data bus on
Port 0. This signal is commonly connected to the latch enable of
an external 373 family transparent latch. In default mode, ALE
has a pulse width of 1.5 XTAL1 cycles and a period of four
XTAL1 cycles. In page mode, the ALE pulse width is altered
according to the page mode selection. ALE is forced high when
using the EMI reduction mode and during a reset condition.
ALE can be enabled by writing ALEON=1 (PMR.2). Note that
ALE operates independently of ALEON during external
memory accesses. As an alternate mode, this pin (
PROG
) is
used to execute the parallel program function
Port 0 (AD0-7) - I/O.
Port 0 is an open-drain 8-bit bidirectional
I/O port. As an alternate function, Port 0 can function as the
multiplexed address/data bus to access off-chip memory.
During the time when ALE is high, the LSB of a memory
address is presented. When ALE falls to a logic 0, the port
transitions to a bidirectional data bus. This bus is used to read
external program memory and read/write external RAM or
peripherals. When used as a memory bus, the port provides
weak pull-ups for logic 1 outputs. The reset condition of Port 0
is tri-state. Pullup resistors are required when using Port 0 as an
I/O port.
Port 1 - I/O.
Port 1 functions as both an 8-bit bidirectional I/O
port and an alternate functional interface for timer 2 I/O, new
external interrupts, and new serial port 1. The reset condition
of Port 1 is with all bits at a logic 1. In this state, a weak pullup
holds the port high. This condition also serves as an input state,
since any external circuit that writes to the port will overcome
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DESCRIPTION
19
18
21
20
15
14
XTAL1
XTAL2
29
32
26
PSEN
30
33
27
ALE/
PROG
39
38
37
36
35
34
33
32
1-8
43
42
41
40
39
38
37
36
2-9
37
36
35
34
33
32
31
30
40-44
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
P1-0-P1-7
DS89C420
DIP
PLCC
TQFP
SIGNAL
NAME
DESCRIPTION
the weak pullup. When software writes a 0 to any port pin, the
DS89C420 activates a strong pulldown that remains on until
either a 1 is written or a reset occurs. Writing a 1 after the port
has been at 0 causes a strong transition driver to turn on,
followed by a weaker sustaining pullup. Once the momentary
strong driver turns off, the port again becomes the output high
(and input) state. The alternate functions of Port 1 are outlined
below:
Port
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Alternate Function
T2
External I/O for timer/Counter2
T2EX Timer 2 Capture/Reload Trigger
RXD1 Serial Port 1 Receive Input
TXD1 Serial Port 1 Transmit Output
INT2 External Interrupt 2 (Positive Edge Detect)
INT3
1
2
3
4
5
6
7
8
21
22
23
24
25
26
27
28
2
3
4
5
6
7
8
9
24
25
26
27
28
29
30
31
40
41
42
43
44
1
2
3
18
19
20
21
22
23
24
25
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0 (A8)
P2.1 (A9)
P2.2(A10)
P2.3(A11)
P2.4(A12)
P2.5(A13)
P2.6(A14)
P2.7(A15)
INT4
INT5
External Interrupt 3 (NegativeEdge Detect)
External Interrupt 4 (Positive Edge Detect)
External Interrupt 5 (NegativeEdge Detect)
Port 2 (A8-15) - I/O.
Port 2 is an 8-bit bidirectional I/O port.
The reset condition of Port 2 is logic high. In this state, a weak
pullup holds the port high. This condition also serves as an
input mode, since any external circuit that writes to the port will
overcome the weak pullup. When software writes a 0 to any
port pin, the DS89C420 activates a strong pulldown that
remains on until either a 1 is written or a reset occurs. Writing
a 1 after the port has been at 0 causes a strong transition driver
to turn on, followed by a weaker sustaining pullup. Once the
momentary strong driver turns off, the port again becomes both
the output high and input state. As an alternate function Port 2
can function as the MSB of the external address bus when
reading external program memory and read/write external
RAM or peripherals. In Page Mode 1, Port 2 provides both the
MSB and LSB of the external address bus and in Page Mode 2,
it provides the MSB and data.
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