FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13727-1E
16-bit Proprietary Microcontroller
CMOS
F
2
MC-16LX MB90435 Series
MB90437L (S) /438L (S) /F438L (S)
MB90439 (S) /F439 (S) /V540G
s
DESCRIPTION
The MB90435 series with FLASH ROM is specially designed for industrial applications.
The instruction set by F
2
MC-16LX CPU core inherits an AT architecture of the F
2
MC* family with additional
instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instruc-
tions, and enhanced bit manipulation instructions.The micro controller has a 32-bit accumulator for processing
long word data.
The MB90435 series has peripheral resources of 8/10-bit A/D converters, UART (SCI) , extended I/O serial
interfaces, 8/16-bit timer, I/O timer (input capture (ICU) , output compare (OCU) ) .
* : F
2
MC stands for FUJITSU Flexible Microcontroller.
s
FEATURES
• Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from : divided-by-2 of oscillation or one to four times the oscillation
Minimum instruction execution time : 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock,
V
CC
of 5.0 V)
Subsystem Clock : 32 kHz
(Continued)
100-pin Plastic QFP
100-pin Plastic LQFP
s
PACKAGES
(FPT-100P-M06)
(FPT-100P-M05)
MB90435 Series
• Instruction set to optimize controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and RETI instruction functions
Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C language) and multi-task operations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
• Program patch function (for two address pointers)
• Enhanced execution speed : 4-byte Instruction queue
• Enhanced interrupt function : 8 levels, 34 factors
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI
2
OS)
• Embedded ROM size and types
Mask ROM : 64 Kbytes / 128 Kbytes / 256 Kbytes
Flash ROM : 128 Kbytes/256 Kbytes
Embedded RAM size : 2 Kbytes/4 Kbytes/6 Kbytes/8 Kbytes (evaluation chip)
• Flash ROM
Supports automatic programming, Embedded Algorithm TM*
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory
Erase can be performed on each block
Block protection with external programming voltage
• Low-power consumption (stand-by) mode
Sleep mode (mode in which CPU operating clock is stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Clock mode
Hardware stand-by mode
• Process
0.5
µm
CMOS technology
• I/O port
General-purpose I/O ports : 81 ports
• Timer
Watchdog timer : 1 channel
8/16-bit PPG timer : 8/16-bit
×
4 channels
16-bit re-load timer : 2 channels
• 16-bit I/O timer
16-bit free-run timer : 1 channel
Input capture : 8 channels
Output compare : 4 channels
• Extended I/O serial interface : 1 channel
• UART 0
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used.
(Continued)
2
MB90435 Series
(Continued)
• UART 1
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized serial (extended I/O serial) can be used.
• External interrupt circuit (8 channels)
A module for starting an extended intelligent I/O service (EI
2
OS) and generating an external interrupt which
is triggered by an external input.
• Delayed interrupt generation module
Generates an interrupt request for switching tasks.
• 8/10-bit A/D converter (8 channels)
8/10-bit resolution can be selectively used.
Starting by an external trigger input.
Conversion time : 26.3
µs
• External bus interface : Maximum address space 16 Mbytes
• Package: QFP-100, LQFP-100
* : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
3
MB90435 Series
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PRODUCT LINEUP
Features
CPU
System clock
MB90F438L (S) /F439 (S)
MB90437L (S) *
1
/438L (S) /439 (S)
F
2
MC-16LX CPU
On-chip PLL clock multiplier (×1,
×2, ×3, ×4,
1/2 when PLL stop)
Minimum instruction exection time : 62.5 ns (4 MHz osc. PLL
×
4)
Flash memory
MB90F438L(S) : 128 Kbytes
MB90F439(S) : 256 Kbytes
MB90F438L(S) : 4 Kbytes
MB90F439(S) : 6 Kbytes
MB90F438L/F439
: Two clocks system
MB90F438LS/F439S
: One clock system
Mask ROM :
MB90437L(S): 64 Kbytes
MB90438L(S): 128 Kbytes
MB90439(S): 256 Kbytes
MB90437L(S): 2 Kbytes
MB90438L(S): 4 Kbytes
MB90439(S): 6 Kbytes
MB90437L/438L/439
: Two clocks system
MB90437LS/438LS/439S
: One clock system
*5
−40 °C
to 105
°C
QFP100, LQFP100
PGA-256
None
External
MB90V540G
ROM
RAM
8 Kbytes
Clocks
Operating voltage
range
Temperature range
Package
Emulator-specify
power supply
*3
UART0
Two clocks system*
2
Full duplex double buffer
Support asynchronous/synchronous (with start/stop bit) transfer
Baud rate : 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous)
500 K/1 M/2 Mbps (synchronous) at System clock
=
16 MHz
Full duplex double buffer
Asynchronous (start-stop synchronized) and CLK-synchronous communication
Baud rate : 1202/2404/4808/9615/19230/31250/38460/62500 bps (asynchronous)
62.5 K/125 K/250 K/500 K/1 M/2 Mbps (synchronous) at 6, 8, 10, 12, 16 MHz
Transfer can be started from MSB or LSB
Supports internal clock synchronized transfer and external clock synchronized transfer
Supports positive-edge and nagative-edge clock synchronization
Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock
=
16 MHz
10-bit or 8-bit resolution
8 input channels
Conversion time : 26.3
µs
(per one channel)
UART1
(SCI)
Serial I/O
A/D Converter
(Continued)
4
MB90435 Series
(Continued)
Features
16-bit Reload Timer
(2 channels)
16-bit I/O Timer
MB90F438L (S) /F439 (S)
MB90437L (S) *
1
/438L (S) /439 (S)
MB90V540G
Operation clock frequency : fsys/2
1
, fsys/2
3
, fsys/2
5
(fsys
=
System clock frequency)
Supports External Event Count function
Signals an interrupt when overflow
Supports Timer Clear when a match with Output Compare (Channel 0)
Operation clock freq. : fsys/2
2
, fsys/2
4
, fsys/2
6
, fsys/2
8
(fsys
=
System clock freq.)
Signals an interrupt when a match with 16-bit I/O Timer
16-bit Output Compare
Four 16-bit compare registers
(4 channels)
A pair of compare registers can be used to generate an output signal
16-bit Input Capture
(8 channels)
Rising edge, falling edge or rising & falling edge sensitive
Four 16-bit Capture registers
Signals an interrupt upon external event
Supports 8-bit and 16-bit operation modes
Eight 8-bit reload counters
Eight 8-bit reload registers for L pulse width
Eight 8-bit reload registers for H pulse width
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit
prescaler plus 8-bit reload counter
4 output pins
Operation clock freq. : fsys, fsys/2
1
, fsys/2
2
, fsys/2
3
, fsys/2
4
or 128
µs@fosc =
4 MHz
(fsys
=
System clock frequency, fosc
=
Oscillation clock frequency)
Sub-clock for low power operation
Can be programmed edge sensitive or level sensitive
External access using the selectable 8-bit or 16-bit bus is enabled
(external bus mode.)
Virtually all external pins can be used as general purpose I/O
All push-pull outputs and schmitt trigger inputs
Bit-wise programmable as input/output or peripheral signal
Supports automatic programming, Embeded Algorithm TM
*4
Write/Erase/Erase-Suspend/Erase-Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Data retention time : 10 years
Boot block configuration
Erase can be performed on each block
Block protection by externally programmed voltage
8/16-bit
Programmable
Pulse Generator
(4 channels)
32 kHz Sub-clock
External Interrupt
(8 channels)
External bus
interface
I/O Ports
Flash Memory
*1 : Under development
*2 : If the one clock system is used, equip X0A and X1A with clocks from the tool side.
*3 : It is setting of DIP switch S2 when Emulator pod (MB2145-507) is used.Please refer to the MB2145-507 hardware
manual (2.7 Emulator-specific Power Pin) about details.
*4 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
*5 : OPERATING VOLTAGE RANGE
Products
Operation guarantee range
MB90F439 (S) /439 (S) /V540G
MB90F438L (S) /437L (S) /438L (S)
4.5 V to 5.5 V
3.5 V to 5.5 V
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Industrial Control Electronics
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