W9751G6NB25I TR datasheet, PDF

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W9751G6NB25I TR: DescriptionSDRAM - DDR2 存储器 IC 512Mb 并联 400 MHz 57.5 ns 84-VFBGA（8x12.5）; Categorysemiconductor memory; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw; Environmental Compliance

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W9751G6NB25I TR Overview

SDRAM - DDR2 存储器 IC 512Mb 并联 400 MHz 57.5 ns 84-VFBGA（8x12.5）

W9751G6NB25I TR Parametric

Parameter Name	Attribute value
category
Maker	Winbond Electronics Corporation
series	-
Package	Tape and Reel (TR)
memory type	Volatile
memory format	DRAM
technology	SDRAM - DDR2
storage	512Mb
memory organization	32M x 16
memory interface	in parallel
Clock frequency	400 MHz
Write cycle time - words, pages	15ns
interview time	57.5 ns
Voltage - Power supply	1.7V ~ 1.9V
Operating temperature	-40°C ~ 95°C（TC）
Installation type	surface mount type
Package/casing	84-VFBGA
Supplier device packaging	84-VFBGA（8x12.5）
Basic product number	W9751G6

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W9751G6NB

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4 BANKS

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16 BIT DDR2 SDRAM

Table of Contents-

8.1

8.2

GENERAL DESCRIPTION ................................................................................................................... 4

FEATURES ........................................................................................................................................... 4

ORDER INFORMATION ....................................................................................................................... 5

KEY PARAMETERS ............................................................................................................................. 5

BALL CONFIGURATION ...................................................................................................................... 6

BALL DESCRIPTION ............................................................................................................................ 7

BLOCK DIAGRAM ................................................................................................................................ 8

FUNCTIONAL DESCRIPTION .............................................................................................................. 9

Power-up and Initialization Sequence ................................................................................................... 9

Mode Register and Extended Mode Registers Operation ................................................................... 10

8.2.1

Mode Register Set Command (MRS)............................................................................... 10

8.2.2

Extend Mode Register Set Commands (EMRS) .............................................................. 11

8.2.2.1

Extend Mode Register Set Command (1), EMR (1) ................................................ 11

8.2.2.2

DLL Enable/Disable ................................................................................................ 12

8.2.2.3

Extend Mode Register Set Command (2), EMR (2)................................................ 13

8.2.2.4

Extend Mode Register Set Command (3), EMR (3) ................................................ 14

8.2.3

Off-Chip Driver (OCD) Impedance Adjustment ................................................................ 15

8.2.3.1

Extended Mode Register for OCD Impedance Adjustment .................................... 16

8.2.3.2

OCD Impedance Adjust .......................................................................................... 16

8.2.3.3

Drive Mode ............................................................................................................. 17

8.2.4

On-Die Termination (ODT) ............................................................................................... 18

8.2.5

ODT related timings ......................................................................................................... 18

8.2.5.1

MRS command to ODT update delay ..................................................................... 18

Command Function ............................................................................................................................. 20

8.3.1

Bank Activate Command.................................................................................................. 20

8.3.2

Read Command ............................................................................................................... 20

8.3.3

Write Command ............................................................................................................... 21

8.3.4

Burst Read with Auto-precharge Command..................................................................... 21

8.3.5

Burst Write with Auto-precharge Command ..................................................................... 21

8.3.6

Precharge All Command .................................................................................................. 21

8.3.7

Self Refresh Entry Command .......................................................................................... 21

8.3.8

Self Refresh Exit Command ............................................................................................. 22

8.3.9

Refresh Command ........................................................................................................... 22

8.3.10

No-Operation Command .................................................................................................. 23

8.3.11

Device Deselect Command.............................................................................................. 23

Read and Write access modes ........................................................................................................... 23

8.4.1

8.4.1.1

Posted

CAS

................................................................................................................... 23

Examples of posted

CAS

operation ..................................................................... 23

8.3

8.4

8.5

8.6

8.4.2

Burst mode operation ....................................................................................................... 24

8.4.3

Burst read mode operation ............................................................................................... 25

8.4.4

Burst write mode operation .............................................................................................. 25

8.4.5

Write data mask ............................................................................................................... 26

Burst Interrupt ..................................................................................................................................... 26

Precharge operation............................................................................................................................ 27

Publication Release Date: Oct. 22, 2019

Revision: A01

-1-

W9751G6NB

8.6.1

Burst read operation followed by precharge..................................................................... 27

8.6.2

Burst write operation followed by precharge .................................................................... 27

8.7

Auto-precharge operation ................................................................................................................... 27

8.7.1

Burst read with Auto-precharge ....................................................................................... 28

8.7.2

Burst write with Auto-precharge ....................................................................................... 28

8.8

Refresh Operation ............................................................................................................................... 29

8.9

Power Down Mode .............................................................................................................................. 29

8.9.1

Power Down Entry ........................................................................................................... 30

8.9.2

Power Down Exit .............................................................................................................. 30

8.10 Input clock frequency change during precharge power down ............................................................. 30

9.1

9.2

9.3

9.4

9.5

10.

OPERATION MODE ........................................................................................................................... 31

Command Truth Table ........................................................................................................................ 31

Clock Enable (CKE) Truth Table for Synchronous Transitions ........................................................... 32

Data Mask (DM) Truth Table ............................................................................................................... 32

Function Truth Table ........................................................................................................................... 33

Simplified Stated Diagram ................................................................................................................... 36

ELECTRICAL CHARACTERISTICS ................................................................................................... 37

10.1 Absolute Maximum Ratings ................................................................................................................ 37

10.2 Operating Temperature Condition ....................................................................................................... 37

10.3 Recommended DC Operating Conditions ........................................................................................... 37

10.4 ODT DC Electrical Characteristics ...................................................................................................... 38

10.5 Input DC Logic Level ........................................................................................................................... 38

10.6 Input AC Logic Level ........................................................................................................................... 38

10.7 Capacitance ........................................................................................................................................ 39

10.8 Leakage and Output Buffer Characteristics ........................................................................................ 39

10.9 DC Characteristics .............................................................................................................................. 40

10.10

IDD Measurement Test Parameters .......................................................................................... 42

10.11

AC Characteristics ..................................................................................................................... 43

10.11.1

AC Characteristics and Operating Condition for -18/18I/18J speed grade ....................... 43

10.11.2

AC Characteristics and Operating Condition for -25/25I/25J/-3/-3I/-3J speed grade ....... 45

10.12

AC Input Test Conditions ........................................................................................................... 66

10.13

Differential Input/Output AC Logic Levels .................................................................................. 66

10.14

AC Overshoot / Undershoot Specification ................................................................................. 67

10.14.1

AC Overshoot / Undershoot Specification for Address and Control Pins: ........................ 67

10.14.2

AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins: ......... 67

11.1

11.2

11.3

11.4

11.5

11.6

11.7

11.8

11.9

11.10

11.11

11.12

11.13

11.14

TIMING WAVEFORMS ....................................................................................................................... 68

Command Input Timing ....................................................................................................................... 68

ODT Timing for Active/Standby Mode ................................................................................................. 69

ODT Timing for Power Down Mode .................................................................................................... 69

ODT Timing mode switch at entering power down mode .................................................................... 70

ODT Timing mode switch at exiting power down mode ...................................................................... 71

Data output (read) timing .................................................................................................................... 72

Burst read operation: RL=5 (AL=2, CL=3, BL=4) ................................................................................ 72

Data input (write) timing ...................................................................................................................... 73

Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4) .................................................................... 73

Seamless burst read operation: RL = 5 ( AL = 2, and CL = 3, BL = 4) ...................................... 74

Seamless burst write operation: RL = 5 ( WL = 4, BL = 4)......................................................... 74

Burst read interrupt timing: RL =3 (CL=3, AL=0, BL=8) ............................................................. 75

Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL=8) .................................................. 75

Write operation with Data Mask: WL=3, AL=0, BL=4) ............................................................... 76

11.

Publication Release Date: Oct. 22, 2019

Revision: A01

-2-

W9751G6NB

11.15

Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=4, tRTP ≤ 2clks) ............ 77

11.16

Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) ............ 77

11.17

Burst read operation followed by precharge: RL=5 (AL=2, CL=3, BL=4, tRTP ≤ 2clks) ............ 78

11.18

Burst read operation followed by precharge: RL=6 (AL=2, CL=4, BL=4, tRTP ≤ 2clks) ............ 78

11.19

Burst read operation followed by precharge: RL=4 (AL=0, CL=4, BL=8, tRTP > 2clks) ............ 79

11.20

Burst write operation followed by precharge: WL = (RL-1) = 3 .................................................. 79

11.21

Burst write operation followed by precharge: WL = (RL-1) = 4 .................................................. 80

11.22

Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) ............... 80

11.23

Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=4, tRTP > 2clks) ............... 81

11.24

Burst read with Auto-precharge followed by an activation to the same bank (tRC Limit): RL=5

(AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks) ....................................................................................... 81

11.25

Burst read with Auto-precharge followed by an activation to the same bank (tRP Limit): RL=5

(AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks)....................................................................................... 82

11.26

Burst write with Auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3 ................................. 82

11.27

Burst write with Auto-precharge (WR + tRP Limit): WL=4, WR=2, BL=4, tRP=3 ....................... 83

11.28

Self Refresh Timing ................................................................................................................... 83

11.29

Basic Power Down Entry and Exit Timing.................................................................................. 84

11.30

Precharged Power Down Entry and Exit Timing ........................................................................ 84

11.31

Clock frequency change in precharge Power Down mode ........................................................ 85

12.

13.

PACKAGE SPECIFICATION .............................................................................................................. 86

REVISION HISTORY .......................................................................................................................... 87

Publication Release Date: Oct. 22, 2019

Revision: A01

-3-

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