• Phase-Lock Loop Clock Distribution for Synchronous DRAM
Applications
• Distributes one clock input to one bank of ten outputs
• Output enable bank control
• External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
• No external RC network required for PLL loop stability
• Operates at 3.3V V
DD
• tpd Phase Error at 166MHz: < ±150ps
• Jitter (peak-to-peak) at 166MHz: < ±75ps @ 166MHz
• Spread Spectrum Compatible
• Operating frequency 50MHz to 175MHz
• Available in 24-Pin TSSOP package
IDTCSP2510D
DESCRIPTION:
The CSP2510D is a high performance, low-skew, low-jitter, phase-lock
loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency
and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CSP2510D
operates at 3.3V.
One bank of ten outputs provide low-skew, low-jitter copies of CLK.
Output signal duty cycles are adjusted to 50 percent, independent of the duty
cycle at CLK. The outputs can be enabled or disabled via the control G input.
When the G input is high, the outputs switch in phase and frequency with
CLK; when the G input is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CSP2510D does not require
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CSP2510D requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as
following any changes to the PLL reference or feedback signals. The PLL
can be bypassed for the test purposes by strapping AV
DD
to ground.
The CSP2510D is specified for operation from 0°C to +85°C. This device
is also available (on special order) in Industrial temperature range (-40°C
to +85°C). See ordering information for details.
APPLICATIONS:
• SDRAM Modules
• PC Motherboards
• Workstations
FUNCTIONAL BLOCK DIAGRAM
11
G
3
Y0
4
Y1
5
Y2
8
Y3
9
Y4
15
Y5
16
Y6
17
CLK
24
PLL
FBIN
13
21
AV
DD
23
12
Y9
20
Y8
Y7
FBOUT
º
º
0ºC TO 85ºC TEMPERATURE RANGE
1
c
2001 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
OCTOBER 2001
DSC-5874/3
IDTCSP2510D
3.3V PHASE-LOCK LOOP CLOCK DRIVER
0
°
C TO 85
°
C TEMPERATURE RANGE
PIN CONFIGURATION
AGND
V
DD
Y0
Y1
Y2
GND
GND
Y3
Y4
V
DD
G
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
TSSOP
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Supply Voltage Range
Input Voltage Range
Voltage range applied to any
output in the high or low state
Input clamp current
Terminal Voltage with Respect
to GND (inputs V
IH
2.5, V
IL
2.5)
Continuous Output Current
Continuous Current
Storage Temperature Range
Junction Temperature
Max
–0.5 to +4.6
–0.5 to +6.5
–0.5 to V
DD
+ 0.5
–50
±50
Unit
V
V
V
mA
mA
24
23
22
21
20
19
18
17
16
15
14
13
CLK
AV
DD
V
DD
Y9
Y8
GND
GND
Y7
Y6
Y5
V
DD
FBIN
V
DD
V
I(1)
V
O(1,2)
I
IK
(V
I
<0)
I
OK
(V
O
<0 or
V
O
> V
DD
)
I
O
(V
O
= 0 to V
DD
)
V
DD
or GND
T
STG
T
J
±50
±100
– 65 to +150
+150
mA
mA
°C
°C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150
°
C and a board trace length of 750 mils.
CAPACITANCE
Parameter
C
IN
C
O
C
L
Description
Input Capacitance
V
I
= V
DD
or GND
Output Capacitance
V
O
= V
DD
or GND
Load Capacitance
Min.
Typ.
5
6
30
Max.
Unit
pF
pF
pF
⎯
⎯
⎯
⎯
⎯
⎯
NOTE:
1. Unused inputs must be held HIGH or LOW to prevent them from floating.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
DD
, AV
DD
T
A
Power Supply Voltage
Operating Free-Air Temperature
Description
Min.
3
0
Max.
3.6
+85
Unit
V
°
C
2
IDTCSP2510D
3.3V PHASE-LOCK LOOP CLOCK DRIVER
0
°
C TO 85
°
C TEMPERATURE RANGE
PIN DESCRIPTION
Terminal
Name
CLK
No.
24
Type
I
Description
Clock input. CLK provides the clock signal to be distributed by the CSP2510D clock driver. CLK is used to provide the reference signal
to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase
lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback
signal to its reference signal.
FBIN
G
FBOUT
Y (0:9)
13
11
12
3, 4, 5, 8, 9,
15, 16, 17,
20, 21
AV
DD
AGND
V
DD
GND
23
1
Power
Ground
Analog power supply. AV
DD
provides the power reference for the analog circuitry. In addition, AV
DD
can be used to bypass the PLL
for test purposes. When AV
DD
is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs.
Analog ground. AGND provides the ground reference for the analog circuitry.
Power supply
Ground
2, 10, 14, 22 Power
6, 7, 18, 19 Ground
I
I
O
O
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The
integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN.
Output bank enable. G is the output enable for outputs Y(0:9). When G is low, outputs Y(0:9) are disabled to a logic-low state. When
G is high, all outputs Y(0:9) are enabled and switch at the same frequency as CLK.
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to
FBIN, FBOUT completes the feedback loop of the PLL.
Clock outputs. These outputs provide low-skew copies of CLK. Output bank Y(0:9) is enabled via the G input. These outputs can be
disabled to a logic-low state by de-asserting the G control input.
STATIC FUNCTION TABLE
(AV
DD
= 0V)
Inputs
G
L
L
H
H
H
CLK
L
H
H
L
running
Y (0:9)
L
L
H
L
running
Outputs
FBOUT
L
H
H
L
running
DYNAMIC FUNCTION TABLE
(AV
DD
= 3.3V)
Inputs
G
X
L
L
H
H
CLK
L
running
H
running
H
Y (0:9)
L
L
L
running in
phase with CLK
H
Outputs
FBOUT
L
running in
phase with CLK
H
running in
phase with CLK
H
3
IDTCSP2510D
3.3V PHASE-LOCK LOOP CLOCK DRIVER
0
°
C TO 85
°
C TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING FREE-AIR TEMPERA-
TURE RANGE
(1)
Symbol
V
IK
V
IH
V
IL
V
OH
Description
Input Clamp Voltage
Input HIGH Level
Input LOW Level
I
OH
= -100μA
HIGH Level Output Voltage
I
OH
= -12mA
I
OH
= -6mA
I
OL
= 100μA
V
OL
I
I
I
DD
ΔI
DD
C
PD
I
DDA
(3)
Test Conditions
I
I
= -18mA
V
DD
3V
⎯
⎯
Min. to Max.
3V
3V
Min. to Max.
3V
3V
3.6V
3.6V
3.3V to 3.6V
3.6V
AV
DD
= 3.3V
Min.
⎯
2
⎯
V
DD
– 0.2
2.1
2.4
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Typ.
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
10
10
(2)
Max.
– 1.2
⎯
0.8
⎯
⎯
⎯
0.2
0.8
0.55
±5
10
500
14
⎯
Unit
V
V
V
V
LOW Level Output Voltage
Input Current
Supply Current
Change in Supply Current
Power Dissipation Capacitance
AV
DD
Power Supply Current
I
OL
= 12mA
I
OL
= 6mA
V
I
= V
DD
or GND
V
I
= V
DD
or GND, AV
DD
= GND,
I
O
= 0, Outputs: LOW or HIGH
One input at V
DD
- 0.6V, other inputs at V
DD
or GND
V
μA
μA
μA
pF
mA
NOTES:
1. For Industrial devices, operating free-air temperature = -40°C to +85°C.
2. For conditions shown as Min. or Max., use the appropriate value specified under recommended operating conditions.
3. For I
DD
of AV
DD
, see TYPICAL CHARACTERISTICS.
TIMING REQUIREMENTS OVER OPERATING RANGE OF SUPPLY VOLTAGE AND
OPERATING FREE-AIR TEMPERATURE
(1)
Min.
Clock frequency
f
CLOCK
Input clock duty cycle
Stabilization time
(2)
50
40%
Max.
175
60%
1
ms
Unit
MHz
⎯
NOTES:
1. For Industrial devices, operating free-air temperature = -40°C to +85°C.
2. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase
reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics
table are not applicable.
4
IDTCSP2510D
3.3V PHASE-LOCK LOOP CLOCK DRIVER
0
°
C TO 85
°
C TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C
L
= 30pF
(1)
V
DD
= 3.3V ± 0.3V
Parameter
(2)
t
PHASE
error
t
PHASE
error – jitter
(3)
t
SK(o)
(4)
Jitter (cycle-cycle)
(peak-to-peak)
Duty cycle reference
(5)
t
R
t
F
CLK = 166MHz
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
45
0.8
0.8
From (Input)
100MHz < CLK↑ < 166MHz
CLK↑ = 166MHz
Any Y (166MHz)
CLK = 166MHz
To (Output)
FBIN↑
FBIN↑
Any Y
Any Y or FBOUT
Min.
– 150
– 50
Typ.
Max.
150
50
150
75
55
2.1
2.5
Unit
ps
ps
ps
ps
%
ns
ns
⎯
– 75
⎯
⎯
⎯
⎯
⎯
⎯
⎯
NOTES:
1. For Industrial devices, operating free-air temperature = -40°C to +85°C. See PARAMETER MEASUREMENT INFORMATION.
2. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
3. Phase error does not include jitter.
4. The t
SK(O)
specification is only valid for equal loading of all outputs.
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