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DM74LS373WM

Description
LS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP20
Categorylogic    logic   
File Size79KB,8 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM74LS373WM Overview

LS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP20

DM74LS373WM Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeSOIC
package instructionSOP, SOP20,.4
Contacts20
Reach Compliance Codeunknow
seriesLS
JESD-30 codeR-PDSO-G20
JESD-609 codee0
length12.8 mm
Load capacitance (CL)45 pF
Logic integrated circuit typeBUS DRIVER
MaximumI(ol)0.024 A
Number of digits8
Number of functions1
Number of ports2
Number of terminals20
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP20,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)40 mA
Prop。Delay @ Nom-Su18 ns
propagation delay (tpd)27 ns
Certification statusNot Qualified
Maximum seat height2.65 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.5 mm
DM74LS373 • DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
April 1986
Revised March 2000
DM74LS373 • DM74LS374
3-STATE Octal D-Type Transparent Latches
and Edge-Triggered Flip-Flops
General Description
These 8-bit registers feature totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high-logic level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the DM74LS373 are transparent D-
type latches meaning that while the enable (G) is HIGH the
Q outputs will follow the data (D) inputs. When the enable
is taken LOW the output will be latched at the level of the
data that was set up.
The eight flip-flops of the DM74LS374 are edge-triggered
D-type flip flops. On the positive transition of the clock, the
Q outputs will be set to the logic states that were set up at
the D inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped-
ance state the outputs neither load nor drive the bus lines
significantly.
The output control does not affect the internal operation of
the latches or flip-flops. That is, the old data can be
retained or new data can be entered even while the outputs
are OFF.
Features
s
Choice of 8 latches or 8 D-type flip-flops in a single
package
s
3-STATE bus-driving outputs
s
Full parallel-access for loading
s
Buffered control inputs
s
P-N-P inputs reduce D-C loading on data lines
Ordering Code:
Order Number
DM74LS373WM
DM74LS373SJ
DM74LS373N
DM74LS374WM
DM74LS374SJ
IDM29901NC
Package Number
M20B
M20D
N20A
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation
DS006431
www.fairchildsemi.com
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