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DM74LS377N

Description
Octal D-Type Flip-Flop with Common Enable and Clock
Categorylogic    logic   
File Size51KB,5 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM74LS377N Overview

Octal D-Type Flip-Flop with Common Enable and Clock

DM74LS377N Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeDIP
package instructionDIP, DIP20,.3
Contacts20
Reach Compliance Codeunknow
Other featuresWITH HOLD MODE
seriesLS
JESD-30 codeR-PDIP-T20
JESD-609 codee0
length26.075 mm
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Su30000000 Hz
MaximumI(ol)0.008 A
Number of digits8
Number of functions1
Number of terminals20
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP20,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)28 mA
propagation delay (tpd)25 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width7.62 mm
minfmax30 MHz
Base Number Matches1
DM74LS377 Octal D-Type Flip-Flop with Common Enable and Clock
October 1988
Revised March 2000
DM74LS377
Octal D-Type Flip-Flop with Common Enable and Clock
General Description
The DM74LS377 is an 8-bit register built using advanced
low power Schottky technology. This register consists of
eight D-type flip-flops with a buffered common clock and a
buffered common input enable. The device is packaged in
the space-saving (0.3 inch row spacing) 20-pin package.
Features
s
8-bit high speed parallel registers
s
Positive edge-triggered D-type flip-flops
s
Fully buffered common clock and enable inputs
Ordering Code:
Order Number
DM74LS377WM
DM74LS377N
Package Number
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
V
CC
=
Pin 20
GND
=
Pin 10
Pin Descriptions
Pin Names
E
D0–D7
CP
Q0–Q7
Description
Enable Input (Active LOW)
Data Inputs
Clock Pulse Input (Active Rising Edge)
Flip-Flop Outputs
Truth Table
Inputs
E
H
L
L
CP
D
n
X
H
L
Output
Q
n
No Change
H
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial


X
© 2000 Fairchild Semiconductor Corporation
DS009831
www.fairchildsemi.com

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