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DM74LS51N

Description
Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gate
Categorylogic    logic   
File Size43KB,4 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM74LS51N Overview

Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gate

DM74LS51N Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeDIP
package instructionDIP, DIP14,.3
Contacts14
Reach Compliance Codeunknown
Other featuresASYMMETRICAL INPUTS
seriesLS
JESD-30 codeR-PDIP-T14
JESD-609 codee0
length19.18 mm
Logic integrated circuit typeAND-OR-INVERT GATE
MaximumI(ol)0.008 A
Number of functions2
Number of entries6
Number of terminals14
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP14,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)2.8 mA
Prop。Delay @ Nom-Sup18 ns
propagation delay (tpd)18 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
Base Number Matches1
DM74LS51 Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gate
August 1986
Revised March 2000
DM74LS51
Dual 2-Wide 2-Input, 2-Wide 3-Input
AND-OR-INVERT Gate
General Description
This device contains two independent combinations of
gates each of which performs the logic AND-OR-INVERT
function. Each package contains one 2-wide 2-input and
one 2-wide 3-input AND-OR-INVERT gates.
Ordering Code:
Order Number
DM74LS51M
DM74LS51N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Y1
=
(A1) (B1) (C1)
+
(D1) (E1) (F1)
Inputs
A1
H
X
B1
H
X
C1
H
X
D1
X
H
E1
X
H
F1
X
H
Output
Y1
L
L
H
Other Combinations
Y2
=
((A2) (B2)
+
(C2) (D2))
Inputs
A2
H
X
B2
H
X
C2
X
H
D2
X
H
Output
Y2
L
L
H
Other combinations
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Either LOW or HIGH Logic Level
© 2000 Fairchild Semiconductor Corporation
DS006369
www.fairchildsemi.com

DM74LS51N Related Products

DM74LS51N 74LS51 DM74LS51M DM74LS51
Description Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gate Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gate Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gate Dual 2-Wide 2-Input, 2-Wide 3-Input AND-OR-INVERT Gate

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