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DM74LS503N

Description
8-Bit Successive Approximation Register (with Expansion Control)
Categorylogic    logic   
File Size41KB,4 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM74LS503N Overview

8-Bit Successive Approximation Register (with Expansion Control)

DM74LS503N Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeDIP
package instructionDIP, DIP16,.3
Contacts16
Reach Compliance Codeunknow
Other featuresSUCCESSIVE APPROXIMATION REGISTER ; Q7 INVERTED OUTPUT ALSO AVAILABLE
Counting directionRIGHT
seriesLS
JESD-30 codeR-PDIP-T16
JESD-609 codee0
length19.305 mm
Logic integrated circuit typeSERIAL IN PARALLEL OUT
Maximum Frequency@Nom-Su15000000 Hz
Number of digits8
Number of functions1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
propagation delay (tpd)25 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width7.62 mm
minfmax15 MHz
DM74LS503 8-Bit Successive Approximation Register
March 1989
Revised March 2000
DM74LS503
8-Bit Successive Approximation Register
(with Expansion Control)
General Description
The DM74LS503 register has an active LOW Enable (E)
input that is used in cascading two or more packages for
longer word lengths. A HIGH signal on E, after a START
operation, forces Q7 HIGH and prevents the device from
accepting serial data. With the E input of an DM74LS503
connected to the CC output of a preceding (more signifi-
cant) device, the DM74LS503 will be inhibited until the pre-
ceding device is filled, causing its CC output to go LOW.
This LOW signal then enables the DM74LS503 to accept
the serial data on subsequent clocks.
Features
s
Performs serial-to-parallel conversion
s
Expansion control for longer words
s
Storage and control for successive approximation A to D
conversion
s
Low power Schottky version of 2503
Ordering Code:
Order Number
DM74LS503N
Package Number
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Logic Symbol
V
CC
=
Pin 16
GND
=
Pin 8
Pin Descriptions
Pin Names
D
S
CP
E
CC
Q0–Q7
Q7
Description
Serial Data Input
Start Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Conversion Enable Input (Active LOW)
Conversion Complete Output (Active LOW)
Parallel Register Outputs
Complement of Q7 Output
© 2000 Fairchild Semiconductor Corporation
DS010190
www.fairchildsemi.com

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