DM74LS645 Octal Bus Transceiver
August 1986
Revised March 2000
DM74LS645
Octal Bus Transceiver
General Description
These octal bus transceivers are designed for asynchro-
nous two-way communication between data buses. The
devices transmit data from the A bus to the B bus or from
the B bus to the A bus depending upon the level at the
direction control (DIR) input. The enable input (G) can be
used to disable the device so that the buses are effectively
isolated.
Features
s
Bi-directional bus transceivers in high-density 20-pin
packages
s
Hysteresis at bus inputs improves noise margins
s
3-STATE outputs
Ordering Code:
Order Number
DM74LS645WM
DM74LS645N
Package Number
M20B
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Control
Inputs
G
L
L
H
H
=
HIGH Level
L
=
LOW Level
X
=
Irrelevant
DM74LS645
DIR
L
H
X
B data to A bus
A data to B bus
Isolation
© 2000 Fairchild Semiconductor Corporation
DS009056
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DM74LS645
Absolute Maximum Ratings
(Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
7V
7V
0°C to
+70°C
−55°C
to
+150°C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
T
A
Parameter
Supply Voltage (Note 2)
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Free Air Operating Temperature
0
Min
4.75
2
0.6
−15
24
70
Nom
5
Max
5.25
Units
V
V
V
mA
mA
°C
Note 2:
Voltage values are with respect to the network ground terminal.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
V
I
H
YS
V
OH
V
OL
I
OZH
I
OZL
I
I
I
IH
I
IL
I
OS
I
CC
Parameter
Input Clamp Voltage
Hysteresis (V
T+
−
V
−
)
A or B Input
HIGH Level Output Voltage
LOW Level Output Voltage
Off-State Output Current,
HIGH Level Voltage Applied
Off-State Output Current,
LOW Level Voltage Applied
Input Current at
Maximum Input Voltage
HIGH Level Input Current
LOW Level Input Current
Total Supply
Current
V
CC
=
Min, V
IH
=
2V,
V
IL
=
Max
V
CC
=
Min, V
IH
=
2V,
V
IL
=
Max
V
CC
=
Max, G at 2V,
V
O
=
2.7V
V
CC
=
Max, G at 2V
V
O
=
0.4V
V
CC
=
Max
A or B
DIR or G
V
CC
=
Max, V
IH
=
2.7
V
CC
=
Max, V
IL
=
0.4V
−40
V
CC
=
Max,
Outputs Open
48
62
64
Outputs HIGH
Outputs LOW
Outputs at Hi-Z
Note 3:
For conditions shown as Min or Max, use the appropriate value specified under Recommended Operating Conditions.
Note 4:
All typicals are at V
CC
=
5V, T
A
=
25°C.
Note 5:
Not more than one output should be shorted at a time, and the duration should not exceed one second.
Conditions (Note 3)
V
CC
=
Min, I
I
=
18 mA
V
CC
=
Min
I
OH
= −3
mA
I
OH
=
Max
I
OL
=
12 mA
I
OL
=
24 mA
Min
Typ
(Note 4)
0.4
3.4
0.25
0.35
Max
−1.5
Units
V
V
0.2
2.4
2
V
0.4
0.5
20
−400
V
µA
µA
mA
µA
mA
mA
mA
V
I
=
5.5V
V
I
=
7V
0.1
0.1
20
−0.4
−225
70
90
95
Short Circuit Output Current (Note 5) V
CC
=
Max
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2
DM74LS645
Switching Characteristics
at V
CC
=
5V and T
A
=
25°C
From (Input)
Symbol
Parameter
To (Output)
C
L
=
45 pF
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZL
t
PZH
t
PZL
t
PZH
t
PLZ
t
PHZ
t
PLZ
t
PHZ
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Output Enable Time
to LOW Level
Output Enable Time
to HIGH Level
Output Enable Time
to LOW Level
Output Enable Time
to HIGH Level
Output Disable Time
to LOW Level
Output Disable Time
to HIGH Level
Output Disable Time
to LOW Level
Output Disable Time
to HIGH Level
A to B
A to B
B to A
B to A
Max
15
15
15
15
R
L
=
667Ω
C
L
=
5 pF
Min
Max
ns
ns
ns
ns
Units
G to A
40
ns
G to A
40
ns
G to B
40
ns
G to B
40
ns
G to A
25
ns
G to A
25
ns
G to B
25
ns
G to B
25
ns
3
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DM74LS645
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
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4
DM74LS645 Octal Bus Transceiver
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
5
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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