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DM74S00M

Description
S SERIES, QUAD 2-INPUT NAND GATE, PDIP14
Categorylogic    logic   
File Size44KB,4 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric Compare View All

DM74S00M Overview

S SERIES, QUAD 2-INPUT NAND GATE, PDIP14

DM74S00M Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeSOIC
package instruction0.150 INCH, MS-120, SOIC-14
Contacts14
Reach Compliance Codeunknow
seriesS
JESD-30 codeR-PDSO-G14
JESD-609 codee0
length8.65 mm
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.02 A
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)36 mA
Prop。Delay @ Nom-Su8 ns
propagation delay (tpd)8 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9 mm
DM74S00 Quad 2-Input NAND Gate
August 1986
Revised May 2000
DM74S00
Quad 2-Input NAND Gate
General Description
This device contains four independent gates each of which
performs the logic NAND function.
Ordering Code:
Order Number
DM74S00M
DM74S00N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Y
=
AB
Inputs
A
L
L
H
H
H
=
HIGH Logic Level
L
=
LOW Logic Level
Output
B
L
H
L
H
Y
H
H
H
L
© 2000 Fairchild Semiconductor Corporation
DS006489
www.fairchildsemi.com

DM74S00M Related Products

DM74S00M DM74S00 DM74S00N
Description S SERIES, QUAD 2-INPUT NAND GATE, PDIP14 S SERIES, QUAD 2-INPUT NAND GATE, PDIP14 S SERIES, QUAD 2-INPUT NAND GATE, PDIP14
series S S S
length 8.65 mm 19.18 mm 19.18 mm
Number of functions 4 4 4
Number of terminals 14 14 14
Maximum operating temperature 70 °C 70 Cel 70 °C
surface mount YES NO NO
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form GULL WING THROUGH-HOLE THROUGH-HOLE
Terminal location DUAL DUAL DUAL
width 3.9 mm 7.62 mm 7.62 mm
Is it Rohs certified? incompatible - incompatible
Maker Fairchild - Fairchild
Parts packaging code SOIC - DIP
package instruction 0.150 INCH, MS-120, SOIC-14 - 0.300 INCH, PLASTIC, MS-001, DIP-14
Contacts 14 - 14
Reach Compliance Code unknow - unknown
JESD-30 code R-PDSO-G14 - R-PDIP-T14
JESD-609 code e0 - e0
Logic integrated circuit type NAND GATE - NAND GATE
MaximumI(ol) 0.02 A - 0.02 A
Number of entries 2 - 2
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY
encapsulated code SOP - DIP
Encapsulate equivalent code SOP14,.25 - DIP14,.3
Package shape RECTANGULAR - RECTANGULAR
Package form SMALL OUTLINE - IN-LINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED - NOT SPECIFIED
power supply 5 V - 5 V
Maximum supply current (ICC) 36 mA - 36 mA
propagation delay (tpd) 8 ns - 8 ns
Certification status Not Qualified - Not Qualified
Schmitt trigger NO - NO
Maximum seat height 1.75 mm - 5.08 mm
Maximum supply voltage (Vsup) 5.25 V - 5.25 V
Minimum supply voltage (Vsup) 4.75 V - 4.75 V
Nominal supply voltage (Vsup) 5 V - 5 V
technology TTL - TTL
Terminal surface Tin/Lead (Sn/Pb) - Tin/Lead (Sn/Pb)
Terminal pitch 1.27 mm - 2.54 mm
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED
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