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DM74LS90M

Description
Decade and Binary Counters
Categorylogic    logic   
File Size54KB,6 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM74LS90M Overview

Decade and Binary Counters

DM74LS90M Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeSOIC
package instructionSOP, SOP14,.25
Contacts14
Reach Compliance Codeunknow
Other featuresDIVIDE BY 2 AND DIVIDE BY 5 FUNCTIONS
Counting directionUP
seriesLS
JESD-30 codeR-PDSO-G14
JESD-609 codee0
length8.6235 mm
Load/preset inputYES
Logic integrated circuit typeDECADE COUNTER
Maximum Frequency@Nom-Su10000000 Hz
MaximumI(ol)0.008 A
Operating modeASYNCHRONOUS
Number of digits3
Number of functions2
Number of terminals14
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)15 mA
propagation delay (tpd)60 ns
Certification statusNot Qualified
Maximum seat height1.753 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typeNEGATIVE EDGE
width3.9 mm
minfmax32 MHz
DM74LS90 Decade and Binary Counters
August 1986
Revised March 2000
DM74LS90
Decade and Binary Counters
General Description
Each of these monolithic counters contains four master-
slave flip-flops and additional gating to provide a divide-by-
two counter and a three-stage binary counter for which the
count cycle length is divide-by-five for the DM74LS90.
All of these counters have a gated zero reset and the
DM74LS90 also has gated set-to-nine inputs for use in
BCD nine’s complement applications.
To use their maximum count length (decade or four bit
binary), the B input is connected to the Q
A
output. The
input count pulses are applied to input A and the outputs
are as described in the appropriate truth table. A symmetri-
cal divide-by-ten count can be obtained from the
DM74LS90 counters by connecting the Q
D
output to the A
input and applying the input count to the B input which
gives a divide-by-ten square wave at output Q
A
.
Features
s
Typical power dissipation 45 mW
s
Count frequency 42 MHz
Ordering Code:
Order Number
DM74LS90M
DM74LS90N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Reset/Count Truth Table
Reset Inputs
R0(1)
H
H
X
X
L
L
X
R0(2)
H
H
X
L
X
X
L
R9(1)
L
X
H
X
L
X
L
R9(2)
X
L
H
L
X
L
X
Q
D
L
L
H
Output
Q
C
L
L
L
Q
B
L
L
L
Q
A
L
L
H
COUNT
COUNT
COUNT
COUNT
© 2000 Fairchild Semiconductor Corporation
DS006381
www.fairchildsemi.com

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