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DM74S02N

Description
Quad 2-Input NOR Gate
Categorylogic    logic   
File Size35KB,3 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM74S02N Overview

Quad 2-Input NOR Gate

DM74S02N Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeDIP
package instructionDIP, DIP14,.3
Contacts14
Reach Compliance Codeunknow
seriesS
JESD-30 codeR-PDIP-T14
JESD-609 codee0
length19.18 mm
Logic integrated circuit typeNOR GATE
MaximumI(ol)0.02 A
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP14,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)45 mA
Prop。Delay @ Nom-Su7.5 ns
propagation delay (tpd)7.5 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
DM74S02 Quad 2-Input NOR Gate
August 1986
Revised May 2000
DM74S02
Quad 2-Input NOR Gate
General Description
This device contains four independent gates each of which
performs the logic NOR function.
Ordering Code:
Order Number
DM74S02N
Package Number
N14A
Package Description
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Function Table
Y
=
A
+
B
Inputs
A
L
L
H
H
H
=
HIGH Logic Level
L
=
LOW Logic Level
Output
B
L
H
L
H
Y
H
L
L
L
© 2000 Fairchild Semiconductor Corporation
DS006490
www.fairchildsemi.com

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