DM74S139N datasheet, PDF - EEWORLD Datasheet

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DM74S139N: DescriptionDecoder/Demultiplexer; Categorylogic logic; File Size54KB，5 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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DM74S139N Overview

Decoder/Demultiplexer

DM74S139N Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Fairchild
Parts packaging code	DIP
package instruction	DIP, DIP16,.3
Contacts	16
Reach Compliance Code	unknow
ECCN code	EAR99
series	S
JESD-30 code	R-PDIP-T16
JESD-609 code	e0
length	19.305 mm
Logic integrated circuit type	OTHER DECODER/DRIVER
MaximumI(ol)	0.02 A
Number of functions	2
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	INVERTED
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP16,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Maximum supply current (ICC)	90 mA
Prop。Delay @ Nom-Su	15 ns
propagation delay (tpd)	15 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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DM74S138 • DM74S139 Decoder/Demultiplexer

August 1986

Revised April 2000

DM74S138 • DM74S139

Decoder/Demultiplexer

General Description

These Schottky-clamped circuits are designed to be used

in high-performance memory-decoding or data-routing

applications, requiring very short propagation delay times.

In high-performance memory systems these decoders can

be used to minimize the effects of system decoding. When

used with high-speed memories, the delay times of these

decoders are usually less than the typical access time of

the memory. This means that the effective system delay

introduced by the decoder is negligible.

The DM74S138 decodes one-of-eight lines, based upon

the conditions at the three binary select inputs and the

three enable inputs. Two active-LOW and one active-HIGH

enable inputs reduce the need for external gates or invert-

ers when expanding. A 24-line decoder can be imple-

mented with no external inverters, and a 32-line decoder

requires only one inverter. An enable input can be used as

a data input for demultiplexing applications.

The DM74S139 comprises two separate two-line-to-four-

line decoders in a single package. The active-LOW enable

input can be used as a data line in demultiplexing applica-

tions.

All of these decoders/demultiplexers feature fully buffered

inputs, presenting only one normalized load to its driving

circuit. All inputs are clamped with high-performance

Schottky diodes to suppress line-ringing and simplify sys-

tem design.

Features

Designed specifically for high speed:

Memory decoders

Data transmission systems

DM74S138 3-to-8-line decoders incorporates 3 enable

inputs to simplify cascading and/or data reception

DM74S139 contains two fully independent 2-to-4-line

decoders/demultiplexers

Schottky clamped for high performance

Typical propagation delay time (3 levels of logic)

DM74S138 8 ns

DM74S139 7.5 ns

Typical power dissipation

DM74S138 245 mW

DM74S139 300 mW

Ordering Code:

Order Number

DM74S138N

DM74S139N

Package Number

N16E

Package Description

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

DS006466

www.fairchildsemi.com

DM74S139N Related Products

	DM74S139N	DM74S139	DM74S138	DM74S138N
Description	Decoder/Demultiplexer	Decoder/Demultiplexer	Decoder/Demultiplexer	Decoder/Demultiplexer

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