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DM74S182N

Description
Look-Ahead Carry Generator
Categorylogic    logic   
File Size47KB,5 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM74S182N Overview

Look-Ahead Carry Generator

DM74S182N Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeDIP
package instructionDIP, DIP16,.3
Contacts16
Reach Compliance Codeunknow
Other featuresWITH HIGHER ORDER LOOKAHEAD
seriesS
JESD-30 codeR-PDIP-T16
JESD-609 codee0
length19.305 mm
Logic integrated circuit typeLOOK-AHEAD CARRY GENERATOR
Number of digits4
Number of functions1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
propagation delay (tpd)11 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
DM74S182 Look-Ahead Carry Generator
August 1986
Revised March 2000
DM74S182
Look-Ahead Carry Generator
General Description
These circuits are high-speed, look-ahead carry genera-
tors, capable of anticipating a carry across four binary
adders or groups of adders. They are cascadable to per-
form full look-ahead across n-bit adders. Carry, generate-
carry, and propagate-carry functions are provided as
shown in the pin designation table.
When used in conjunction with the 181 arithmetic logic unit,
these generators provide high-speed carry look-ahead
capability for any word length. Each DM74S182 generates
the look-ahead (anticipated carry) across a group of four
ALU’s and, in addition, other carry look-ahead circuits may
be employed to anticipate carry across sections of four
look-ahead packages up to n-bits. The method of cascad-
ing circuits to perform multi-level look-ahead is illustrated
under typical application data.
Carry input and output of the ALU’s are in their true form,
and the carry propagate (P) and carry generate (G) are in
negated form; therefore, the carry functions (inputs, out-
puts, generate, and propagate) of the look-ahead genera-
tors are implemented in the compatible forms for direct
connection to the ALU. Reinterpretations of carry functions,
as explained on the 181 data sheet are also applicable to
and compatible with the look-ahead generator. Positive
logic equations for the DM74S182 are:
C
n
+
x
=
G0
+
P0 C
n
C
n
+
y
=
G1
+
P1 G0
+
P1 P0 C
n
C
n
+
z
=
G2
+
P2 G1
+
P2 P1 G0
+
P2 P1 P0 C
n
G
=
G3 (P3
+
G2) (P3
+
P2
+
G1)
(P3
+
P2
+
P1
+
G0)
P
=
P3 P2 P1 P0
Features
s
Typical propagation delay time 7 ns
s
Typical power dissipation 260 mW
Ordering Code:
Order Number
DM74S182N
Package Number
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Pin Designations
Designation
G0, G1, G2, G3
P0, P1, P2, P3
C
n
C
n
+
x
, C
n
+
y
,
C
n
+
z
G
P
V
CC
GND
10
7
16
8
Active LOW
Carry Generate Output
Active LOW
Carry Propagate Output
Supply Voltage
Ground
Pin Nos.
3, 1, 14, 5
4, 2, 15, 6
13
12, 11, 9
Function
Active LOW
Carry Generate Inputs
Active LOW
Carry Propagate Inputs
Carry Input
Carry Outputs
© 2000 Fairchild Semiconductor Corporation
DS006474
www.fairchildsemi.com

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