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DM74S253N

Description
Dual 3-STATE 1-of-4 Line Data Selector/Multiplexer
Categorylogic    logic   
File Size48KB,4 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM74S253N Overview

Dual 3-STATE 1-of-4 Line Data Selector/Multiplexer

DM74S253N Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeDIP
package instruction0.300 INCH, PLASTIC, MS-001, DIP-16
Contacts16
Reach Compliance Codeunknown
seriesS
JESD-30 codeR-PDIP-T16
JESD-609 codee0
length19.305 mm
Logic integrated circuit typeMULTIPLEXER
MaximumI(ol)0.02 A
Number of functions2
Number of entries4
Output times1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)70 mA
Prop。Delay @ Nom-Sup12 ns
propagation delay (tpd)12 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
Base Number Matches1
DM74S253 Dual 3-STATE 1-of-4 Line Data Selector/Multiplexer
August 1986
Revised May 2000
DM74S253
Dual 3-STATE 1-of-4 Line Data Selector/Multiplexer
General Description
Each of these Schottky-clamped data selectors/multiplex-
ers contains inverters and drivers to supply fully comple-
mentary, on-chip, binary decoding data selection to the
AND-OR gates. Separate output control inputs are pro-
vided for each of the two four-line sections.
The 3-STATE outputs can interface directly with data lines
of bus-organized systems. With all but one of the common
outputs disabled (at a high impedance state), the low
impedance of the single enable output will drive the bus
line to a HIGH or LOW logic level.
Features
s
3-STATE version of S153 with same pin-out
s
Schottky-diode-clamped transistors
s
Permits multiplexing from N lines to 1 line
s
Performs parallel-T-serial conversion
s
Strobe/output control
s
High fan-out totem-pole outputs
s
Typical propagation delay
From data to output
From select to output
6 ns
12 ns
s
Typical power dissipation 275 mW
Ordering Code:
Order Number
DM74S253N
Package Number
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Function Table
Select
Inputs
B
X
L
L
L
L
H
H
H
H
A
X
L
L
H
H
L
L
H
H
C0
X
L
H
X
X
X
X
X
X
C1
X
X
X
L
H
X
X
X
X
C2
X
X
X
X
X
L
H
X
X
C3
X
X
X
X
X
X
X
L
H
Data Inputs
Output
Control
G
H
L
L
L
L
L
L
L
L
Y
Z
L
H
L
H
L
H
L
H
Output
Address inputs A and B are common to both sections.
H
=
HIGH Level
L
=
LOW Level
X
=
Don’t Care
Z
=
High Impedance
© 2000 Fairchild Semiconductor Corporation
DS006481
www.fairchildsemi.com

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