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DM74S299N

Description
3-STATE 8-Bit Universal Shift/Storage Register
Categorylogic    logic   
File Size58KB,5 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM74S299N Overview

3-STATE 8-Bit Universal Shift/Storage Register

DM74S299N Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeDIP
package instructionDIP, DIP20,.3
Contacts20
Reach Compliance Codeunknow
Other featuresHOLD MODE
Counting directionBIDIRECTIONAL
seriesS
JESD-30 codeR-PDIP-T20
JESD-609 codee0
length26.075 mm
Logic integrated circuit typePARALLEL IN PARALLEL OUT
Maximum Frequency@Nom-Su40000000 Hz
Number of digits8
Number of functions1
Number of terminals20
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP20,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
propagation delay (tpd)23 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width7.62 mm
minfmax50 MHz
Base Number Matches1
DM74S299 3-STATE 8-Bit Universal Shift/Storage Register
August 1986
Revised May 2000
DM74S299
3-STATE 8-Bit Universal Shift/Storage Register
General Description
This Schottky TTL eight-bit universal register features mul-
tiplexed inputs/outputs to achieve full eight bit data han-
dling in a single 20-pin package. Two function-select inputs
and two output-control inputs can be used to choose the
modes of operation listed in the function table.
Synchronous parallel loading is accomplished by taking
both function-select lines, S0 and S1, HIGH. This places
the 3-STATE outputs in a high-impedance state, which per-
mits data that is applied on the input/output lines to be
clocked into the register. Reading out of the register can be
accomplished while the outputs are enabled in any mode.
A direct overriding input is provided to clear the register
whether the outputs are ENABLED or OFF.
Features
s
Multiplexed inputs/outputs provide improved bit density
s
Four modes of operation:
Hold (Store)
Shift Right
Shift Left
Load Data
s
3-STATE outputs drive bus lines directly
s
Can be cascaded for N-bit word lengths
s
Operates with outputs enabled or at high Z
s
Guaranteed shift (clock) frequency 50 MHz
s
Typical power dissipation 700 mW
Ordering Code:
Order Number
DM74S299N
Package Number
N20A
Package Description
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
© 2000 Fairchild Semiconductor Corporation
DS006485
www.fairchildsemi.com

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DM74S299N DM74S299
Description 3-STATE 8-Bit Universal Shift/Storage Register 3-STATE 8-Bit Universal Shift/Storage Register

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