DM93L14 Quad Latch
June 1989
Revised November 1999
DM93L14
Quad Latch
General Description
The DM93L14 is a multifunctional 4-bit latch designed for
general purpose storage applications in high speed digital
systems. All outputs have active pull-up circuitry to provide
high capacitance drive and to provide low impedance in
both logic states for good noise immunity.
Features
s
Can be used as single input D latches or set/reset
latches
s
Active low enable gate input
s
Overriding master reset
Ordering Code:
Order Number
DM93L14N
Package Number
N14A
Package Description
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Logic Symbol
Connection Diagram
V
CC
=
Pin 16
GND
=
Pin 8
Pin Descriptions
Pin Names
E
D0
−
D3
S0
−
S3
MR
Q0
−
Q3
Description
Enable Input (Active LOW)
Data Inputs
Set Inputs (Active LOW)
Master Reset Input (Active LOW)
Latch Outputs
© 1999 Fairchild Semiconductor Corporation
DS009612
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DM93L14
Functional Description
The DM93L14 consists of four latches with a common
active LOW Enable input and active LOW Master Reset
input. When the Enable goes HIGH, data present in the
latches is stored and the state of the latch is no longer
affected by the S
n
and D
n
inputs. the Master Reset when
activated overrides all other input conditions forcing all
latch outputs LOW. Each of the four latches can be oper-
ated in one of two modes:
D-TYPE LATCH—For D-type operation the S input of a
latch is held LOW. While the common Enable is active the
latch output follows the D input. Information present at the
latch output is stored in the latch when the Enable goes
HIGH.
SET/RESET LATCH—During set/reset operation when the
common Enable is LOW a latch is reset by a LOW on the D
input, and can be set by a LOW on the S input if the D input
is HIGH. If both S and D inputs are LOW, the D input will
dominate and the latch will be reset. When the Enable
goes HIGH, the latch remains in the last state prior to dis-
ablement. The two modes of latch operation are shown in
the Truth Table.
Truth Table
MR
H
H
H
H
H
H
H
H
L
E
L
L
H
L
L
L
L
H
X
D
L
H
X
L
H
L
H
X
X
S
L
L
X
L
L
H
H
X
X
Q
n
L
L
Q
n-1
L
H
L
Q
n-1
Q
n-1
L
RESET
R/S Mode
Operation
D Mode
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Q
n−1
=
Previous Output State
Q
n
=
Present Output State
Logic Diagram
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2
DM93L14
Absolute Maximum Ratings
(Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
7V
5.5V
0°C to
+70°C
−65°C
to
+150°C
Note 1:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The Recommended Operating Conditions table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
T
A
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
H
(L)
t
W
(L)
t
W
(L)
t
REC
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
LOW Level Output Current
Free Air Operating Temperature
Setup Time HIGH or LOW
D
n
to
E
Hold Time HIGH or LOW
D
n
to
E
Setup time HIGH, D
n
to
S
n
Hold time LOW, D
n
to
S
n
Parameter
Min
4.5
2
0.7
Nom
5
Max
5.5
Units
V
V
V
−
400
4.8
µ
A
mA
−
55
10
20
0
10
15
5
30
25
5
125
°
C
ns
ns
ns
ns
ns
ns
ns
E Pulse Width LOW
MR Pulse Width LOW
Recovery time,
MR
to
E
3
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DM93L14
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
V
I
V
OH
V
OL
I
I
I
IH
I
IL
I
OS
I
CC
Parameter
Input Clamp Voltage
HIGH Level Output Voltage
LOW Level Output Voltage
Input Current @ Max
Input Voltage
HIGH Level Input Current
LOW Level Input Current
Short Circuit
Output Current
Supply Current
Note 2:
All typicals are at V
CC
=
5V, T
A
=
25°C
Note 3:
Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 4:
I
CC
is measured with all outputs open and all inputs grounded.
Conditions
V
CC
=
Min, I
I
= −10
mA
V
CC
=
Min, I
OH
=
Max,
V
IL
=
Max, V
IH
=
Min
V
CC
=
Min, I
OL
=
Max,
V
IH
=
Min, V
IL
=
Max
V
CC
=
Max, V
I
=
5.5V
V
CC
=
Max, V
I
=
2.4V
V
CC
=
Max, V
I
=
0.3V
V
CC
=
Max
(Note 3)
V
CC
=
Max (Note 4)
Inputs
D
n
Inputs
D
n
Min
Typ
(Note 2)
Max
−1.5
Units
V
V
2.4
0.3
1
20
30
−400
−600
−2.5
−25
16.5
V
mA
µA
µA
mA
mA
Switching Characteristics
V
CC
= +
5.0V, T
A
= +25°C
(See Waveforms and Load Configurations)
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Propagation Delay
E to Q
n
Propagation Delay
D
n
to Q
n
Propagation Delay, MR to Q
n
Propagation Delay, S
n
to Q
n
Parameter
Min
Max
45
36
30
30
30
33
Units
ns
ns
ns
ns
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4
DM93L14 Quad Latch
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
5
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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