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DM93S62N

Description
9-Input Parity Checker/Generator
Categorylogic    logic   
File Size53KB,5 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM93S62N Overview

9-Input Parity Checker/Generator

DM93S62N Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeDIP
package instruction0.300 INCH, PLASTIC, MS-001, DIP-14
Contacts14
Reach Compliance Codeunknow
Other featuresODD/EVEN PARITY GENERATOR
seriesS
JESD-30 codeR-PDIP-T14
JESD-609 codee0
length19.18 mm
Logic integrated circuit typePARITY GENERATOR/CHECKER
Number of digits9
Number of functions1
Number of terminals14
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP14,.3
Package shapeRECTANGULAR
Package formIN-LINE
power supply5 V
propagation delay (tpd)26 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width7.62 mm
DM93S62 9-Input Parity Checker/Generator
October 1988
Revised May 2000
DM93S62
9-Input Parity Checker/Generator
General Description
The DM93S62 is a very high speed 9-input parity checker/
generator for use in error detection and error correction
applications. The DM93S62 provides odd and even parity
for up to nine data bits. The even parity output (PE) is
HIGH if an even number of inputs are HIGH and E is LOW.
The odd parity output (PO) will be HIGH if an odd number
of inputs are HIGH and E is LOW. A HIGH level on the
Enable (E) input forces both outputs LOW.
Ordering Code:
Order Number
DM93S62N
Package Number
N14A
Package Description
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Logic Symbol
Connection Diagram
V
CC
=
Pin 14
GND
=
Pin 7
Pin Descriptions
Pin Name
I0–I8
E
PO
PE
Data Inputs
Output Enable (Active LOW)
Odd Parity Output
Even Parity Output
Description
Truth Table
(E
=
LOW)
Number of Inputs
I0–I8 that are HIGH
1, 3, 5, 7, 9
0, 2, 4, 6, 8
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Outputs
PO
H
L
PE
L
H
© 2000 Fairchild Semiconductor Corporation
DS009809
www.fairchildsemi.com

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