DM96L02 Dual Retriggerable Resettable Monostable Multivibrator
March 1989
Revised February 2000
DM96L02
Dual Retriggerable Resettable Monostable Multivibrator
General Description
The DM96L02 is a dual TTL monostable multivibrator with
trigger mode selection, reset capability, rapid recovery,
internally compensated reference levels and high speed
capability. Output pulse duration and accuracy depend on
external timing components, and are therefore under user
control for each application. It is well suited for a broad vari-
ety of applications, including pulse delay generators,
square wave generators, long delay timers, pulse absence
detectors, frequency detectors, clock pulse generators and
fixed-frequency dividers. Each input is provided with a
clamp diode to limit undershoot and minimize ringing
induced by fast fall times acting on system wiring imped-
ances.
Features
s
Retriggerable, 0% to 100% duty cycle
s
DC level triggering, insensitive to transition times
s
Leading or trailing-edge triggering
s
Complementary outputs with active pull-ups
s
Pulse width compensation for
∆V
CC
and
∆T
A
s
50 ns to
∞
output pulse width range
s
Optional retrigger lock-out capability
s
Resettable, for interrupt operations
Ordering Code:
Order Number
DM96L02N
Package Number
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Logic Symbol
Connection Diagram
V
CC
=
Pin 16
GND
=
Pin 8
Pin Descriptions
Pin Names
I0
I1
C
D
Q
Q
CX
RX
Description
Trigger Input (Active Falling Edge)
Trigger Input (Active Rising Edge)
Direct Clear Input (Active LOW)
Positive Pulse Output
Complementary Pulse Output
External Capacitor Connection
External Resistor Connection
© 2000 Fairchild Semiconductor Corporation
DS010203
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DM96L02
Functional Block Diagram
Operation Notes
1. TRIGGERING—can be accomplished by a positive-
going transition on pin 4 (12) or a negative-going transi-
tion on pin 5 (11). Triggering begins as a signal crosses
the input V
IL
:V
IH
threshold region; this activates an
internal latch whose unbalanced cross-coupling causes
it to assume a preferred state. As the latch output goes
LOW it disables the gates leading to the Q output and,
through an inverter, turns on the capacitor discharge
transistor. The inverted signal is also fed back to the
latch input to change its state and effectively end the
triggering action; thus the latch and its associated feed-
back perform the function of a differentiator.
The emitters of the latch transistors return to ground
through an enabling transistor which must be turned off
between successive triggers in order for the latch to
proceed through the proper sequence when triggering
is desired. Pin 5 (11) must be HIGH in order to trigger
at pin 4 (12); conversely, pin 4 (12) must be LOW in
order to trigger at pin 5 (11).
2. RETRIGGERING—In a normal cycle, triggering ini-
tiates a rapid discharge of the external timing capacitor,
followed by a ramp voltage run-up at pin 2 (14). The
delay will time out when the ramp voltage reaches the
upper trigger point of a Schmitt circuit, causing the out-
puts to revert to the quiescent state. If another trigger
occurs before the ramp voltage reaches the Schmitt
threshold, the capacitor will be discharged and the
ramp will start again without having disturbed the out-
put. The delay period can therefore be extended for an
arbitrary length of time by insuring that the interval
between triggers is less than the delay time, as deter-
mined by the external capacitor and resistor.
3. NON-RETRIGGERABLE OPERATION—Retriggering
can be inhibited logically, by connecting pin 6 (10) back
to pin 4 (12) or by connecting pin 7 (9) back to pin 5
(11). Either hook-up has the effect of keeping the latch-
enabling transistor turned on during the delay period,
which prevents the input latch from cycling as dis-
cussed above in the section on triggering.
4. OUTPUT PULSE WIDTH—An external resistor R
X
and
an external capacitor C
X
are required, as shown in the
functional block diagram. To minimize stray capaci-
tance and noise pickup, R
X
and C
X
should be located
as close as possible to the circuit. In applications which
require remote trimming of the pulse width, as with a
variable resistor, R
X
should consist of a fixed resistor in
series with the variable resistor; the fixed resistor
should be located as close as possible to the circuit.
The output pulse width t
W
is defined as follows, where
R
X
is in kΩ, C
X
is in pF and t
W
is in ns.
t
W
=
0.33 R
X
C
X
(1
+
3/R
X
) for C
X
≥
10
3
pF
16 kΩ
≤
R
X
≤
220 kΩ for 0°C to
+75°C
20 kΩ
≤
R
X
≤
100 kΩ for
−55°C
to
+125°C
C
X
may vary from 0 to any value. For pulse widths with
C
X
less than 10
3
pF see Figure 1.
5. SETUP AND RELEASE TIMES—The setup times
listed below are necessary to allow the latch-enabling
transistor to turn off and the node voltages within the
input latch to stabilize, thus insuring proper cycling of
the latch when the next trigger occurs. The indicated
release times (equivalent to trigger duration) allow time
for the input latch to cycle and its signal to propagate.
6. RESET OPERATION—A LOW signal on C
D
, pin 3
(13), will terminate an output pulse, causing Q to go
LOW and Q to go HIGH. As long as C
D
is held LOW, a
delay period cannot be initiated nor will attempted trig-
gering cause spikes at the outputs. A reset pulse dura-
tion, in the LOW state, of 25 ns is sufficient to insure
resetting. If the reset input goes LOW at the same time
that a trigger transition occurs, the reset will dominate
and the outputs will not respond to the trigger. If the
reset input goes HIGH coincident with a trigger transi-
tion, the circuit will respond to the trigger.
Input to Pin 5 (11)
Pin 4 (12)
=
L
Pin 3 (13)
=
H
Input to Pin 4 (12)
Pins 5 (11) and 3 (13)
=
H
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