DM96LS02 Dual Retriggerable Resettable Monostable Multivibrator
October 1988
Revised March 2000
DM96LS02
Dual Retriggerable Resettable Monostable Multivibrator
General Description
The DM96LS02 is a dual retriggerable and resettable
monostable multivibrator. The one-shot provides excep-
tionally wide delay range, pulse width stability, predictable
accuracy and immunity to noise. The pulse width is set by
an external resistor and capacitor. Resistor values up to 1.0
MΩ reduce required capacitor values. Hysteresis is pro-
vided on both trigger inputs of the DM96LS02 for increased
noise immunity.
Features
s
Required timing capacitance reduced by factors of 10 to
100 over conventional designs
s
Broad timing resistor range—1.0 kΩ to 2.0 MΩ
s
Output Pulse Width is variable over a 2000:1 range by
resistor control
s
Propagation delay of 35 ns
s
0.3V hysteresis on trigger inputs
s
Output pulse width independent of duty cycle
s
35 ns to
∞
output pulse width range
Ordering Code:
Order Number
DM96LS02M
DM96LS02N
Package Number
M16A
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
V
CC
=
Pin 16
GND
=
Pin 8
Pin Descriptions
Pin
Names
I0
I0
I1
C
D
Q
Q
Description
Trigger Input (Active Falling Edge)
Schmitt Trigger Input (Active Falling Edge)
Schmitt Trigger Input (Active Rising Edge)
Direct Clear Input (Active LOW)
True Pulse Output
Complementary Pulse Output
© 2000 Fairchild Semiconductor Corporation
DS009816
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DM96LS02
Functional Description
The DM96LS02 dual retriggerable resettable monostable
multivibrator has two DC coupled trigger inputs per func-
tion, one active LOW (I0) and one active HIGH (I1). The I1
input and I0 input of the DM96LS02 utilize an internal
Schmitt trigger with hysteresis of 0.3V to provide increased
noise immunity. The use of active HIGH and LOW inputs
allows either rising or falling edge triggering and optional
non-retriggerable operation. The inputs are DC coupled
making triggering independent of input transition times.
When input conditions for triggering are met, the Q output
goes HIGH and the external capacitor is rapidly discharged
and then allowed to recharge. An input trigger which occurs
during the timing cycle will retrigger the circuit and result in
Q remaining HIGH. The output pulse may be terminated (Q
to the LOW state) at any time by setting the Direct Clear
input LOW. Retriggering may be inhibited by tying the Q
output to I0 or the Q output to I1. Differential sensing tech-
niques are used to obtain excellent stability over tempera-
ture and power supply variations and a feedback
Darlington capacitor discharge circuit minimizes pulse
width variation from unit to unit. Schottky TTL output stages
provide high switching speeds and output compatibility with
all TTL logic families.
Logic Diagram
Operation Notes
TIMING
1. An external resistor (R
X
) and an external capacitor (C
X
)
are required as shown in the Logic Diagram. The value of
R
X
may vary from 1.0 kΩ to 1.0 MΩ.
2. The value of C
X
may vary from 0 to any necessary value
available. If, however, the capacitor has significant leakage
relative to V
CC
/R
X
the timing equations may not represent
the pulse width obtained.
3. The output pulse width t
W
for R
X
≥
10 kΩ and C
X
≥
1000 pF is determined as follows:
t
W
=
0.43 R
X
C
X
Where R
X
is in kΩ, C
X
is in pF, t is in ns
or
R
X
is in kΩ, C
X
is in
µF,
t is in ms.
4. The output pulse width for R
X
<
10 kΩ or C
X
<
1000 pF
should be determined from pulse width versus C
X
or R
X
graphs.
5. To obtain variable pulse width by remote trimming, the
following circuit is recommended:
TRIGGERING
1. The minimum negative pulse width into I0 is 8.0 ns; the
minimum positive pulse width into I1 is 12 ns.
2. Input signals to the DM96LS02 exhibiting slow or noisy
transitions can use either trigger as both are Schmitt trig-
gers.
3. When non-retriggerable operation is required, i.e., when
input triggers are to be ignored during quasi-stable state,
input latching is used to inhibit retriggering.
4. An overriding active LOW level direct clear is provided
on each multivibrator. By applying a LOW to the clear, any
timing cycle can be terminated or any new cycle inhibited
until the LOW reset input is removed. Trigger inputs will not
produce spikes in the output when the reset is held LOW. A
LOW-to-HIGH transition on C
D
will not trigger the
DM96LS02. If the C
D
input goes HIGH coincident with a
trigger transition, the circuit will respond to the trigger.
6. Under any operating condition, C
X
and R
X
(Min) must be
kept as close to the circuit as possible to minimize stray
capacitance and reduce noise pickup.
7. V
CC
and ground wiring should conform to good high fre-
quency standards so that switching transients on V
CC
and
ground leads do not cause interaction between one shots.
Use of a 0.01
µF
to 0.1
µF
bypass capacitor between V
CC
and ground located near the circuit is recommended.
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2
DM96LS02
Absolute Maximum Ratings
(Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
7V
7V
0°C to
+70°C
−65°C
to
+150°C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
T
A
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Free Air Operating Temperature
0
Parameter
Min
4.75
2
0.8
−0.4
8
70
Nom
5
Max
5.25
Units
V
V
V
mA
mA
°C
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted)
Symbol
V
I
V
OH
V
OL
Parameter
Input Clamp Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
I
I
I
IH
I
IL
I
OS
I
CC
V
T+
V
T−
Input Current @ Max
Input Voltage
HIGH Level Input Current
LOW Level Input Current
Short Circuit Output Current
Supply Current
Positive-Going Threshold
Voltage, I0, I1
Negative-Going Threshold
Voltage, I0, I1
Note 2:
All typicals are at V
CC
=
5V, T
A
=
25°C.
Note 3:
Not more than one output should be shorted at a time, and the duration should not exceed one second.
Conditions
V
CC
=
Min, I
I
= −18
mA
V
CC
=
Min, I
OH
=
Max,
V
IL
=
Max
V
CC
=
Min, I
OL
=
Max,
V
IH
=
Min
I
OL
=
4 mA, V
CC
=
Min
V
CC
=
Max, V
I
=
7V
V
I
=
10V
V
CC
=
Max, V
I
=
2.7V
V
CC
=
Max, V
I
=
0.4V
V
CC
=
Max (Note 3)
V
CC
=
Max
Min
Typ
(Note 2)
Max
−1.5
Units
V
V
2.7
3.4
0.35
0.25
0.5
0.4
0.1
20
−0.4
V
mA
µA
mA
mA
mA
V
V
−20
−100
36
2.0
0.8
5
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