1:12 LVDS 1.8V / 2.5V Fanout Buffer
for 1PPS and High-Speed Clocks
8P34S1212
Datasheet
Description
The 8P34S1212 is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of 1PPS signals or
high-frequency, very low additive phase-noise clock and data
signals. The 8P34S1212 is characterized to operate from a
1.8V or 2.5V power supply. Guaranteed output-to-output and
part-to-part skew characteristics make the 8P34S1212 ideal for
those clock distribution applications that demand well-defined
performance and repeatability.
Two selectable differential inputs and 12 low skew outputs are
available. The integrated bias voltage reference enables easy
interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Features
•
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•
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12 low skew, low additive jitter LVDS output pairs
Two selectable, differential clock input pairs
Differential CLK0, CLK1 pairs can accept the following
differential input levels: LVDS, CML
Maximum input clock frequency: 1.5GHz (maximum)
LVCMOS/LVTTL interface levels for the control input select pin
Output skew: 10ps (typical)
Propagation delay: 400ps (maximum)
Low propagation delay variation across temperature for 1PPS
applications
Low additive phase jitter, RMS; f
REF
= 156.25MHz, V
PP
= 1V,
12kHz– 20MHz: 34fs (typical)
Maximum device current consumption (I
DD
): 185mA typ at 1.8V
or 200mA typ at 2.5V
Full 1.8V or 2.5V supply voltage
Lead-free (RoHS 6), 40-Lead VFQFPN packaging
-40°C to +85°C ambient operating temperature
Supports case temperature up to +105°C
Supports PCI Express Gen 1-5
Block Diagram
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
f
REF
V
DD
Pin Assignment
GND
30
29
28
27
26
25
24
23
22
V
DD
31
Q8
32
nQ8
33
Q9
34
nQ9
35
Q10
36
nQ10
37
Q11
38
nQ11
39
V
DD
40
1
2
3
4
5
6
7
8
9
10
GND
21
20
V
DD
19
nQ3
18
Q3
17
nQ2
16
Q2
15
nQ1
14
Q1
13
nQ0
12
Q0
11
V
DD
nQ7
nQ6
nQ5
nQ4
nCLK0
Q7
Q6
Q5
8P34S1212
40-Lead VFQFPN
6.0mm x 6.0mm x 0.90mm
package body
4.65mm x 4.65mm ePad Size
NL Package
Top View
V
DD
CLK0
nCLK0
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
VREF
CLK1
nCLK1
CLK0
SEL
V
DD
SEL
Q9
nQ9
Q10
nQ10
V
REF
V
REF
Q11
nQ11
©2021 Renesas Electronics Corporation
1
V
DD
nc
nc
CLK1
nCLK1
Q4
August 30, 2021
8P34S1212 Datasheet
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
[a]
Number
1
2
3
4, 10
5, 6, 11, 20,
31, 40
7
8
9
12, 13
14, 15
16, 17
18, 19
21, 30
22, 23
24, 25
26, 27
28, 29
32, 33
34, 35
36, 37
38, 39
[a]
Name
SEL
CLK1
nCLK1
nc
V
DD
V
REF
nCLK0
CLK0
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
GND
Q4, nQ4
Q5, nQ5
Q6, nQ6
Q7, nQ7
Q8, nQ8
Q9, nQ9
Q10, nQ10
Q11, nQ11
Input
Input
Output
Output
Output
Output
Power
Output
Output
Output
Output
Output
Output
Output
Output
Pulldown/
Pullup
Pulldown
Input
Input
Input
Unused
Power
Type
Pulldown
Pulldown
Pulldown/
Pullup
Description
Reference select control. See Table 3 for function.
LVCMOS/LVTTL interface levels.
Non-inverting differential clock/data input.
Inverting differential clock/data input.
Do not connect.
Power supply pins.
Bias voltage reference. Provides an input bias voltage for the CLKx,
nCLKx input pairs in AC-coupled applications. Refer to
Figures 2B and
2C
for applicable AC-coupled input interfaces.
Inverting differential clock/data input.
Non-inverting differential clock/data input.
Differential output pair 0. LVDS interface levels.
Differential output pair 1. LVDS interface levels.
Differential output pair 2. LVDS interface levels.
Differential output pair 3. LVDS interface levels.
Power supply ground.
Differential output pair 4. LVDS interface levels.
Differential output pair 5. LVDS interface levels.
Differential output pair 6. LVDS interface levels.
Differential output pair 7. LVDS interface levels.
Differential output pair 8. LVDS interface levels.
Differential output pair 9. LVDS interface levels.
Differential output pair 10. LVDS interface levels.
Differential output pair 11. LVDS interface levels.
Pulldown
and
Pullup
refers to an internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Table 3. SEL Input Function Table
[a]
Input
SEL
0 (Default)
1
[a]
Operation
CLK0, nCLK0 is the selected differential clock input.
CLK1, nCLK1 is the selected differential clock input.
SEL is an asynchronous control.
©2021 Renesas Electronics Corporation
2
August 30, 2021
8P34S1212 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC
Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Input Sink/Source, I
REF
Maximum Junction Temperature, T
J,MAX
Storage Temperature, T
STG
ESD - Human Body Model
[a]
ESD - Charged Device Model
Note 1.
[a]
According to JEDEC JS-001-2012/JESD11-C101E.
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
±2mA
125°C
-65°C to 150°C
2000V
1500V
DC Electrical Characteristics
Table 4. Power Supply DC Characteristics,
V
DD
= 1.8V ±5%, T
A
= -40°C to +85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Q0 to Q3 terminated 100 between nQx, Qx
Test Conditions
Minimum
1.71
Typical
1.8
185
Maximum
1.89
227
Units
V
mA
Table 5. Power Supply DC Characteristics,
V
DD
= 2.1V – 2.7V, T
A
= -40°C to +85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Q0 to Q3 terminated 100 between nQx, Qx
Test Conditions
Minimum
2.1
Typical
2.5
200
Maximum
2.7
242
Units
V
mA
©2021 Renesas Electronics Corporation
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August 30, 2021
8P34S1212 Datasheet
Table 6. LVCMOS/LVTTL DC Characteristics,
V
DD
= 1.8V ±5%, 2.1V – 2.7V, T
A
= -40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage, Note 1
Input High Current
Input Low Current
SEL
SEL
V
DD
= V
IN
= 1.89V, 2.7V
V
DD
= 1.89V, 2.7V, V
IN
= 0V
-10
Test Conditions
Minimum
0.65 * V
DD
-0.3
Typical
Maximum
V
DD
+ 0.3
0.35 * V
DD
150
Units
V
V
µA
µA
Note 1: VIL should not be less than -0.3V and VIH should not be higher than V
DD
.
Table 7. Differential Inputs Characteristics,
V
DD
= 1.8V ±5%, 2.1V – 2.7V, T
A
= -40°C to +85°C
Symbol
I
IH
Parameter
Input
High Current
Input
Low Current
CLK0, nCLK0,
CLK1, nCLK1
CLK0, CLK1
nCLK0, nCLK1
Test Conditions
V
IN
= V
DD
= 1.89V, 2.7V
V
IN
= 0V, V
DD
= 1.89V, 2.7V
V
IN
= 0V, V
DD
= 1.89V, 2.7V
I
REF
= +100µA, V
DD
= 1.8V, 2.5V
V
DD
= 1.89V, 2.7V
-10
-150
0.9
0.2
0.9
1.30
1.0
V
DD
– (V
PP
/2)
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
I
IL
V
REF
V
PP
V
CMR
[a]
[b]
[c]
Reference Voltage for Input
Bias
[a]
Peak-to-Peak Voltage
Common Mode Input Voltage
[b]
[c]
V
REF
specification is applicable to the AC-coupled input interfaces shown in
Figures 2B and 2C.
Common mode input voltage is defined as crosspoint voltage.
V
IL
should not be less than -0.3V and V
IH
should not be higher than V
DD
.
Table 8. LVDS AC and DC Characteristics,
V
DD
= 1.8V ±5%, 2.1V – 2.7V, T
A
= -40°C to +85°C
[a]
Symbol
V
OD
V
OD
V
OD
V
OS
V
OS
V
OS
[a]
Parameter
Differential Output Voltage
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
Offset Voltage
V
OS
Magnitude Change
V
DD
= 1.8V ±5%
V
DD
= 2.1V – 2.7V
1.00
1.50
Test Conditions
f
REF
< 1.5GHz,
outputs loaded with 100
f
REF
< 500MHz,
outputs loaded with 100
Minimum
247
310
Typical
Maximum
454
454
50
1.40
2.10
50
Units
mV
mV
mV
V
V
mV
Output drive current must be sufficient to drive up to 30cm of PCB trace (assume nominal 50 impedance).
©2021 Renesas Electronics Corporation
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August 30, 2021
8P34S1212 Datasheet
AC Electrical Characteristics
Table 9. AC Electrical Characteristics,
V
DD
= 1.8V ±5%, 2.1V – 2.7V, T
A
= -40°C to +85°C
[a]
Symbol
f
REF
V/t
t
PD
tsk(o)
tsk(i)
tsk(p)
tsk(pp)
Parameter
Input
Frequency
Input
Edge Rate
CLK[0:1],
nCLK[0:1]
CLK[0:1],
nCLK[0:1]
CLK[0:1]; nCLK[0:1] to any Qx, nQx
1.5
200
340
10
5
f
REF
= 100MHz
f
REF
= 156.25MHz; square wave,
V
DD
= 1.8V ± 5%, 2.1V
–
2.7V, V
PP
= 0.5V;
Integration range: 1kHz – 40MHz
f
REF
= 156.25MHz square wave,
V
DD
= 1.8V ± 5%, 2.1V
–
2.7V, V
PP
= 1V;
Integration range: 12kHz – 20MHz
10% to 90%,
outputs loaded with 100
20% to 80%,
outputs loaded with 100
f
REF
= 100MHz
3
450
45
45
20
250
45
34
225
110
72.6
63
47
400
260
Test Conditions
Minimum
Typical
Maximum
1.5
Units
GHz
V/ns
ps
ps
ps
ps
ps
fs
fs
ps
ps
dB
Propagation Delay
[b] [c]
Output Skew
[d] [e]
Input Skew
Note 5.
Pulse Skew
Part-to-Part Skew
[f]
Buffer Additive Phase
Jitter, RMS; refer to
Additive Phase Jitter
Section
t
JIT
t
R
/ t
F
MUX
ISOLATION
[a]
[b]
[c]
[d]
[e]
[f]
[g]
Output Rise/ Fall Time
Mux Isolation
[g]
Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equi-
librium has been reached under these conditions.
Measured from the differential input crossing point to the differential output crossing point
Input V
PP
= 400mV
Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.
This parameter is defined in accordance with JEDEC Standard 65.
Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Qx, nQx outputs measured differentially. See
MUX Isolation diagram
in the
Parameter Measurement Information section.
©2021 Renesas Electronics Corporation
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August 30, 2021
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