PIC32MK GENERAL PURPOSE AND
MOTOR CONTROL (GPG/MCJ)
WITH CAN FD FAMILY
32-bit General Purpose and Motor Control Application MCUs with
CAN FD, FPU, ECC Flash, and up to 512 KB Flash, 64 KB SRAM, and
Op amps
Operating Conditions: 2.3V to 3.6V
• -40ºC to +85ºC, DC to 120 MHz
• -40ºC to +125ºC, DC to 80 MHz
Security Features
• Advanced Memory Protection:
- Peripheral and memory region access control
Core: 120 MHz (up to 198 DMIPS)
•
microAptiv™ MCU core with Floating Point Unit
• microMIPS™ mode for up to 40% smaller code size
• DSP-enhanced core:
- Four 64-bit accumulators
- Single-cycle MAC, saturating and fractional math
• Code-efficient (C and Assembly) architecture
• Two 32-bit core register files to reduce interrupt latency
MIPS32
®
Advanced Analog Features
• 12-bit ADC module:
- Sum of all individual ADCs combined, 25.45 Msps 12-bit
mode or 33.79 Msps 8-bit mode
- 7 individual ADC modules
- 3.75 Msps per S&H with dedicated DMA
- Up to 30 analog inputs
• Flexible and independent ADC trigger sources
• Four high bandwidth op-amps and five comparators
• Up to two 12-bit CDACs
• Internal temperature sensor ±2ºC accuracy
• Capacitive Touch Divider (CVD)
Clock Management
• 8 MHz ±4% (FRC) internal oscillator -40ºC to +85ºC
• Programmable PLLs and oscillator clock sources:
- HS and EC clock modes
• 32 kHz Internal Low-power RC oscillator (LPRC)
• Independent external low-power 32 kHz crystal oscillator
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timers (WDT) and Deadman Timer
(DMT)
• Fast wake-up and start-up
• Four Fractional clock out (REFCLKO) modules
Communication Interfaces
• CAN Flexible Data-Rate (CAN FD) module (with dedicated DMA
channels):
- 2.0B Active with DeviceNet™ addressing support
- ISO 11898-1:2015 compliant
• Up to two UART modules (up to 25 Mbps):
- Supports LIN 2.1 and IrDA
®
protocols
• Two SPI/I
2
S modules (SPI 50 Mbps)
• Two I
2
C modules (up to 1 Mbaud) with SMBus support
• Peripheral Pin Select (PPS) to enable remappable pin functions
Power Management
• Low-power management modes (Sleep, and Idle)
• Integrated:
- Power-on Reset (POR) and Brown-out Reset (BOR)
- Programmable High/Low Voltage Detect (HLVD)
• On-board capacitorless regulator
Timers/Output Compare/Input Capture/RTCC
• Up to nine 16-bit or one 16-bit and eight 32-bit timers/counters
for GP and MC devices and two additional QEI 32-bit timers for
MC devices
• 9 Output Compare (OC) modules
• 9 Input Capture (IC) modules
• PPS to enable function remap
• Real-Time Clock and Calendar (RTCC) module
Motor Control PWM
Up to nine PWM pairs
Leading-edge and Trailing-edge blanking
Dead Time for rising and falling edges
Dead Time Compensation
8.33 ns PWM Resolution
Clock Chopping for High-Frequency Operation
PWM Support for:
- DC/DC, AC/DC, inverters, PFC, lighting
- BLDC, PMSM, ACIM, SRM motors
• Choice of 10 Fault and 9 Current Limit Inputs
• Flexible Trigger Configuration for ADC Triggering
•
•
•
•
•
•
•
Input/Output
•
•
•
•
5V-tolerant pins with up to 22 mA source/sink
Selectable internal open drain, pull-ups, and pull-downs
External interrupts on all I/O pins
Five programmable edge/level-triggered interrupt pins
Motor Encoder Interface
• Three Quadrature Encoder Interface (QEI) modules:
- Four inputs: Phase A, Phase B, Home, and Index
Qualification and Class B Support
•
•
•
•
Class B Safety Library, IEC 60730 (planned)
Back-up internal oscillator
Clock monitor with back-up internal oscillator
Global register locking
Audio/Graphics/Touch Interfaces
• Up to two I
2
S audio data communication interfaces
• Up to two SPI control interfaces
• Programmable master clock:
- Generation of fractional clock frequencies
- Can be tuned in run-time
Debugger Development Support
•
•
•
•
•
In-circuit and in-application programming
2-wire or 4-wire MIPS
®
Enhanced JTAG interface
Unlimited software and 12 complex breakpoints
IEEE 1149.2-compatible (JTAG) boundary scan
Non-intrusive hardware-based instruction trace
Unique Features
• Permanent non-volatile 4-word unique device serial number
• Flash Error Code Correction (ECC)
Software and Tools Support
•
•
•
•
•
C/C++ compiler with native DSP/fractional support
MPLAB
®
Harmony Integrated Software Framework
TCP/IP, Graphics, and mTouch™ middleware
MFi, Android™ and Bluetooth
®
audio frameworks
RTOS Kernels: Express Logic ThreadX, FreeRTOS™,
OPENRTOS
®
, Micriµm
®
µC/OS™, and SEGGER embOS
®
Direct Memory Access (DMA)
• Up to eight channels with automatic data size detection
• Programmable Cyclic Redundancy Check (CRC)
• Up to 64 KB transfers
2019-2020 Microchip Technology Inc.
DS60001570C -page 1
PIC32MK GPG/MCJ with CAN FD Family
Device Pin Tables
TABLE 2:
PIN NAMES FOR 64-PIN GENERAL PURPOSE (GPG) DEVICES
64-PIN QFN
(4)
AND TQFP (TOP VIEW)
PIC32MK0512GPG064
PIC32MK0256GPG064
64
QFN
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Note
TCK/RPA7/RA7
RPB14/RB14
RPB15/RB15
AN19/CVD19/RPG6/RG6
AN18/CVD18/RPG7/RG7
AN17/CVD17/RPG8/RG8
MCLR#
AN16/CVD16/RPG9/RG9
VSS
VDD
AN10/CVD10/RPA12/RA12
AN9/CVD9/RPA11/RA11
OA2OUT/AN0/C2IN4-/C4IN3-/RPA0/RA0
OA2IN+/AN1/C2IN1+/RPA1/RA1
PGD3/VREF-/OA2IN-/AN2/C2IN1-/RPB0/CTED2/RB0
PGC3/OA1OUT/VREF+/AN3/C1IN4-/C4IN2-/RPB1/CTED1/RB1
PGC1/OA1IN+/AN4/C1IN1+/C1IN3-/C2IN3-/RPB2/RB2
PGD1/OA1IN-/AN5/CTCMP/C1IN1-/RTCC/RPB3/RB3
AVDD
AVSS
OA3OUT/AN6/CVD6/C3IN4-/C4IN1+/C4IN4-/RPC0/RC0
OA3IN-/AN7/CVD7/C3IN1-/C4IN1-/RPC1/RC1
OA3IN+/AN8/CVD8/C3IN1+/C3IN3-/RPC2/RC2
AN11/CVD11/C1IN2-/RC11
VSS
VDD
AN12/CVD12/C2IN2-/C5IN2-/RE12
AN13/CVD13/C3IN2-/RE13
AN14/CVD14/RPE14/RE14
AN15/CVD15/RPE15/RE15
TDI/DAC2/AN26/CVD26/RPA8/SDA2/RA8
RPB4/SCL2/RB4
1:
2:
3:
4:
5:
Full Pin Name
(4)
1
64
TQFP
Full Pin Name
1
Pin #
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
OA5IN+/AN24/CVD24/C5IN1+/C5IN3-/RPA4/RA4
AN40/CVD40/RPE0/RE0
AN41/CVD41/RPE1/RE1
AN46/CVD46/RPA14/RA14
AN47/CVD47/RPA15/RA15
VDD
OSCI/CLKI/AN49/CVD49/RPC12/RC12
OSCO/CLKO/RPC15/RC15
VSS
RD8
PGD2/RPB5/SDA1/RB5
PGC2/RPB6/SCL1/RB6
DAC1/AN48/CVD48/RPC10/RC10
OA5OUT/AN25/CVD25/C5IN4-/RPB7/SCK1/INT0/RB7
SOSCI/RPC13
(5)
/RC13
(5)
SOSCO/RPB8
(5)
/T1CK
(5)
/RB8
(5)
TMS/OA5IN-/AN27/CVD27/LVDIN/C5IN1-/RPB9/RB9
TRCLK/RPC6/RC6
TRD0/RPC7/RC7
TRD1/RPC8/RC8
TRD2/RPD5/RD5
TRD3/RPD6/RD6
RPC9/RC9
VSS
VDD
RPF0/RF0
RPF1/RF1
RPB10/RB10
RPB11/RB11
RPB12/RB12
RPB13/CTPLS/RB13
TDO/RA10
The RPn pins can be used by remappable peripherals. See
Table 1
for the available peripherals and
10.3 “Peripheral Pin Select
(PPS)”
for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See
10.0 “I/O Ports”
for more information.
Shaded pins are 5V tolerant.
The metal heat sink pad at the bottom of the device is not connected to any pins and is recommended to be connected to V
SS
externally.
Functions are restricted to input functions only and inputs will be slower than the standard inputs. Change notification interrupt is
not available on this pin.
DS60001570C-page 4
2019-2020 Microchip Technology Inc.
PIC32MK GPG/MCJ with CAN FD Family
TABLE 3:
PIN NAMES FOR 64-PIN MOTOR CONTROL (MCJ) DEVICES
64-PIN QFN
(4)
AND TQFP (TOP VIEW)
PIC32MK0512MCJ064
PIC32MK0256MCJ064
64
64
QFN
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Note
Full Pin Name
TCK/RPA7/PWM4L/RA7
RPB14/PWM1H/RB14
RPB15/PWM1L/RB15
AN19/CVD19/RPG6/PWM7L/RG6
AN18/CVD18/RPG7/PWM7H/RG7
AN17/CVD17/RPG8/RG8
MCLR#
AN16/CVD16/RPG9/FLT12/RG9
VSS
VDD
AN10/CVD10/RPA12/FLT13/RA12
AN9/CVD9/RPA11/FLT14/RA11
OA2OUT/AN0/C2IN4-/C4IN3-/RPA0/RA0
OA2IN+/AN1/C2IN1+/RPA1/RA1
PGD3/VREF-/OA2IN-/AN2/C2IN1-/RPB0/CTED2/RB0
PGC3/OA1OUT/VREF+/AN3/C1IN4-/C4IN2-/RPB1/CTED1/RB1
PGC1/OA1IN+/AN4/C1IN1+/C1IN3-/C2IN3-/RPB2/RB2
PGD1/OA1IN-/AN5/CTCMP/C1IN1-/RTCC/RPB3/RB3
AVDD
AVSS
OA3OUT/AN6/CVD6/C3IN4-/C4IN1+/C4IN4-/RPC0/RC0
OA3IN-/AN7/CVD7/C3IN1-/C4IN1-/RPC1/RC1
OA3IN+/AN8/CVD8/C3IN1+/C3IN3-/RPC2/FLT3/RC2
AN11/CVD11/C1IN2-/FLT4/RC11
VSS
VDD
AN12/CVD12/C2IN2-/C5IN2-/FLT5/RE12
AN13/CVD13/C3IN2-/FLT6/RE13
AN14/CVD14/RPE14/FLT7/RE14
AN15/CVD15/RPE15/FLT8/RE15
TDI/DAC2/AN26/CVD26/RPA8/SDA2/RA8
FLT15/RPB4/SCL2/RB4
1:
2:
3:
4:
5:
Pin #
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
(4)
1
TQFP
Full Pin Name
1
OA5IN+/AN24/CVD24/C5IN1+/C5IN3-/RPA4/RA4
AN40/CVD40/RPE0/RE0
AN41/CVD41/RPE1/RE1
AN46/CVD46/RPA14/RA14
AN47/CVD47/RPA15/RA15
VDD
OSCI/CLKI/AN49/CVD49/RPC12/RC12
OSCO/CLKO/RPC15/RC15
VSS
RD8
PGD2/RPB5/SDA1/RB5
PGC2/RPB6/SCL1/RB6
DAC1/AN48/CVD48/RPC10/RC10
OA5OUT/AN25/CVD25/C5IN4-/RPB7/SCK1/INT0/RB7
SOSCI/RPC13
(5)
/RC13
(5)
SOSCO/RPB8
(5)
/T1CK
(5)
/RB8
(5)
TMS/OA5IN-/AN27/CVD27/LVDIN/C5IN1-/RPB9/RB9
TRCLK/RPC6/PWM6H/RC6
TRD0/RPC7/PWM6L/RC7
TRD1/RPC8/PWM5H/RC8
TRD2/RPD5/PWM9H/RD5
TRD3/RPD6/PWM9L/RD6
RPC9/PWM5L/RC9
VSS
VDD
RPF0/PWM8H/RF0
RPF1/PWM8L/RF1
RPB10/PWM3H/RB10
RPB11/PWM3L/RB11
RPB12/PWM2H/RB12
RPB13/PWM2L/CTPLS/RB13
TDO/PWM4H/RA10
The RPn pins can be used by remappable peripherals. See
Table 1
for the available peripherals and
10.3 “Peripheral Pin Select (PPS)”
for restrictions.
Every I/O port pin (RAx-RGx) can be used as a change notification pin. See
10.0 “I/O Ports”
for more information.
Shaded pins are 5V tolerant.
The metal heat sink pad on the bottom of the QFN device is not connected to any pins and is recommended to be connected to VSS
externally.
Functions are restricted to input functions only and inputs will be slower than standard inputs. Change notification interrupt is not avail-
able on this pin.
2019-2020 Microchip Technology Inc.
DS60001570C-page 5