DNC3X3625 datasheet, PDF - EEWORLD Datasheet

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DNC3X3625: DescriptionHex 10/100 Mbits/s Ethernet Transceiver Macrocell; File Size291KB，32 Pages; ManufacturerAgere System(LSI Logic)

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DNC3X3625 Overview

Hex 10/100 Mbits/s Ethernet Transceiver Macrocell

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Advance Data Sheet

March 2000

DNC3X3625

Hex 10/100 Mbits/s Ethernet Transceiver Macrocell

Features

Hex 10 Mbits/s Transceiver

Hex 100 Mbits/s FX Transceiver

Compatible with

IEEE

802.3u 100Base-FX stan-

dard.

Reuses existing twisted-pair I/O pins for compatible

fiber-optic transceiver pseudo-ECL (PECL) data.

Fiber mode automatically configures port:

— FX mode enable is pin or register selectable

— Disables autonegotiation and 10Base-T.

— Enables 100Base-FX remote fault signaling.

— Disables MLT-3 encoder/decoder.

— Disables scrambler/descrambler.

DSP based.

Compatible with

IEEE

* 802.3 10Base-T standard

for twisted-pair cable.

Half- and full-duplex operations.

Autopolarity detection and correction.

Adjustable squelch level for extended wire-length

capability (two levels).

Interfaces with

IEEE

802.3u media independent

interface (MII) or a serial 10 Mbits/s 7-pin interface.

On-chip filtering eliminates the need for external fil-

ters.

General

Ports individually configurable

Autonegotiation and management:

— Fast link pulse (FLP) burst generator.

— Arbitration function.

— Accepts preamble suppression.

— Operates up to 12.5 MHz.

Supports the MII station management protocol and

frame format (clause 22): basic and extended reg-

ister set.

Supports next page.

Provides status signals: receive activity, transmit

activity, full duplex, collision/jabber, link integrity,

and speed indication.

Powerdown mode for 10 Mbits/s and 100 Mbits/s

operation.

Loopback testing for 10 Mbits/s and 100 Mbits/s

operation.

0.25

µm

low-power CMOS technology.

Single 3.3 V power supply operation.

25 MHz XTAL oscillator input or 25 MHz/50 MHz/

125 MHz clock input.

Compatible with RMII (standard version) and SMII

(standard version).

Hex 100 Mbits/s Transceiver

Compatible with

IEEE

802.3u MII (clause 22),

PCS/PMA (clause 24), PMD (clause 25), MII man-

agement, and autonegotiation (clause 28) specifi-

cations.

Selectable 5-bit code-group (PDT/PDR interface)

or 4-bit data nibbles (MII interface) input/output.

Full- or half-duplex operations.

Optional carrier integrity monitor (CIM).

Selectable carrier sense signal generation (MCRS)

asserted during either transmission or reception in

half duplex (MCRS asserted during reception only

in full duplex).

Adaptive equalization and baseline wander correc-

tion.

On-chip filtering eliminates the need for external

filters.

IEEE

is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

Note: Advisories are issued as needed to update product information. When using this data sheet for design purposes, please contact

your Lucent Technologies Microelectronics Group Account Manager to obtain the latest advisory on this product.

DNC3X3625

10/100 Mbits/s Ethernet Transceiver Macrocell

Advance Data Sheet

March 2000

Table of Contents

Contents

Page

Features .................................................................................................................................................................... 1

Hex 10 Mbits/s Transceiver ..................................................................................................................................... 1

Hex 100 Mbits/s Transceiver ................................................................................................................................... 1

Hex 100 Mbits/s FX Transceiver.............................................................................................................................. 1

General ................................................................................................................................................................... 1

Description ................................................................................................................................................................ 4

Functional Block Diagram .......................................................................................................................................4

Macrocell I/Os ......................................................................................................................................................... 5

Signal Information...................................................................................................................................................... 6

Signal Descriptions ................................................................................................................................................. 6

MII Station Management .........................................................................................................................................13

Basic Operation ....................................................................................................................................................13

MII Interface Design ................................................................................................................................................14

Absolute Maximum Ratings.....................................................................................................................................14

Electrical Characteristics .........................................................................................................................................15

Register Information ................................................................................................................................................19

Register Descriptions............................................................................................................................................19

Application Notes: Board Layout .............................................................................................................................31

Board Layout Considerations ................................................................................................................................31

Tables

Page

Table 1. MII/5-Bit Serial Interface Signals................................................................................................................. 6

Table 2. MII Management Signals ............................................................................................................................ 7

Table 3. 10/100 Mbits/s Twisted-Pair (TP) Interface Signals..................................................................................... 7

Table 4. Status Signals .............................................................................................................................................8

Table 5. Clock and Reset Signals ............................................................................................................................. 9

Table 6. Control/Status Signals ..............................................................................................................................10

Table 7. Testability Signals......................................................................................................................................12

Table 8. MII Management Frame Format................................................................................................................13

Table 9. MII Management Frames—Field Description............................................................................................13

Table 10 . Absolute Maximum Ratings ...................................................................................................................14

Table 11 . Operating Conditions .............................................................................................................................14

Table 12. Summary of Management Registers (MR) .............................................................................................19

Table 13. MR0—Control Register Bit Descriptions .................................................................................................20

Table 14. MR1—Status Register Bit Descriptions ..................................................................................................21

Table 15. MR2, MR3—PHY Identification Registers (1 and 2) Bit Descriptions .....................................................22

Table 16. MR4—Autonegotiation Advertisement Register Bit Descriptions............................................................22

Table 17. MR5—Autonegotiation Link Partner Ability (Base Page) Register Bit Descriptions................................23

Table 18. MR5—Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Descriptions .........................23

Table 19. MR6—Autonegotiation Expansion Register Bit Descriptions..................................................................24

Table 20. MR7—Next Page Transmit Register Bit Descriptions..............................................................................25

Table 21. MR16—PCS Control Register Bit Descriptions.......................................................................................25

Table 22. MR17—Autonegotiation Read Register A...............................................................................................26

Table 23. MR18—Autonegotiation Read Register B...............................................................................................26

Table 24. MR20—User-Defined Register ...............................................................................................................27

Table 25. MR21—RXER Counter ...........................................................................................................................27

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