Datasheet
Class-AB Speaker Amplifier Series
1.2 W
Monaural Speaker Amplifier for Automotive
BD783xxEFJ-M Series (Including products under development)
General Description
BD783xxEFJ-M Series are Class-AB monaural speaker
amplifiers designed for automotive. Class-AB amplifiers
have no requirements for care about EMI noise. Adopting
power package HTSOP-J8 achieves high output power.
Low quiescent current can reduce battery consumption.
Shutdown current is also very low (0.1 µA Typ) and pop
noise level when switching to shutdown is very small, so
this device is suitable for applications in which the mode
often changes between “shutdown state” and “active
state”.
Key Specifications
Output Power
1.2 W (Typ)
(VDD = 5 V, R
L
= 8 Ω, THD+N = 1 %)
Quiescent Current
2.5 mA (Typ)
Shutdown Current
0.1 µA (Typ)
Total Harmonic Distortion + Noise
(R
L
= 8 Ω, f = 1 kHz)
0.05 % (Typ)
(Note 2)
Output Noise Voltage
15 μV
RMS
(Typ)
(Note 2)
Voltage Gain
6.0 dB to 26.0 dB (Typ)
Operating Temperature Range -40 ºC to +105 ºC
W (Typ) x D (Typ) x H (Max)
4.90 mm x 6.00 mm x 1.00 mm
(Note 2)
Characteristic of BD78306EFJ-M
Features
AEC-Q100 Qualified
(Note 1)
Pop Noise Reduction Function
Shutdown Function
Protection Functions
-
Over Current Protection
-
Thermal Shutdown
-
Under Voltage Lock Out (UVLO)
Power Package with Thermal Pad HTSOP-J8
Package
HTSOP-J8
(Note 1)
Grade2
Applications
Automotive Instruments
HTSOP-J8
Typical Application Circuit
1
SDB
From System
Control
OUTN
8
C
1
0.47 µF
2
BIAS
GND
7
C
4
10 µF
3
INP
Input
Signal
C
2
0.47 µF
VDD
6
VDD
C
3
4
INN
OUTP
5
0.47 µF
Figure 1
〇Product
structure : Silicon integrated circuit
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© 2019 ROHM Co., Ltd. All rights reserved.
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〇This
product has no designed protection against radioactive rays.
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BD783xxEFJ-M Series (Including products under development)
Pin Configuration
(TOP VIEW)
SDB
BIAS
INP
INN
1
2
3
4
EXP-PAD
8
7
6
5
OUTN
GND
VDD
OUTP
Caution:
VDD and GND pins adjoin each other. In case that these pins are shorted each other, it may make characteristics of power
supply device worse, or it may damage power supply device.
Considering this point, select power supply device which has protection functions as over current protection.
Pin Description
Pin No.
1
2
3
4
5
6
7
8
-
Pin Name
SDB
BIAS
INP
INN
OUTP
VDD
GND
OUTN
EXP-PAD
Shutdown
Bias
Positive differential input
Negative differential input
Positive output
Power supply
Ground
Negative output
Connect the EXP-PAD to Ground
Function
Control Pin’s Setting
SDB pin
High
Low
Operating Mode
Active
Shutdown
Block Diagram
6
VDD
Rf
Part Number
BD78306EFJ-M
OUTP
Ri
INP
Ri
Rf
Rf
Ri
[
kΩ
]
(Typ)
90
80
70
60
50
40
36
30
24
20
16
Rf
[
kΩ
]
(Typ)
90
80
110
120
130
140
144
150
156
160
164
5
BD78308EFJ-M
*1
BD78310EFJ-M
BD78312EFJ-M
*1
BD78314EFJ-M
*1
BD78316EFJ-M
*1
BD78318EFJ-M
*1
3
Ri
OUTN
INN
Ri
Rf
BIAS
Over Current
Pro tection
Thermal
Shu tdo wn
8
4
BD78320EFJ-M
*1
BD78322EFJ-M
*1
BD78324EFJ-M
*1
BD78326EFJ-M
*1 Under Development
2
Bias
SDB
GND
Under Vol tage
Lock O ut
1
7
Figure 2
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BD783xxEFJ-M Series (Including products under development)
Absolute Maximum Ratings (Ta = 25 °C)
Parameter
Supply Voltage
Input Voltage
Storage Temperature Range
Maximum Junction Temperature
Symbol
VDDmax
Vin
Tstg
Tjmax
Rating
7.0
-0.3 to VDD+0.3
-55 to +150
150
Unit
V
V
°C
°C
Caution 1:
Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2:
Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by increasing
board size and copper area so as not to exceed the maximum junction temperature rating.
Thermal Resistance
(Note 1)
Parameter
HTSOP-J8
Junction to Ambient
Junction to Top Characterization Parameter
(Note 2)
θ
JA
Ψ
JT
149.4
11.0
39.8
9.0
°C/W
°C/W
Symbol
Thermal Resistance (Typ)
1s
(Note 3)
2s2p
(Note 4)
Unit
(Note 1)
Based on JESD51-2A (Still-Air), using a BD78326EFJ-M Chip.
(Note 2)
The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
surface of the component package.
(Note 3)
Using a PCB board based on JESD51-3.
(Note 4)
Using a PCB board based on JESD51-5, 7.
Layer Number of
Measurement Board
Single
Top
Copper Pattern
Footprints and Traces
Layer Number of
Measurement Board
4 Layers
Top
Copper Pattern
Footprints and Traces
Material
FR-4
Thickness
70 μm
Material
FR-4
Thickness
70 μm
Board Size
114.3 mm x 76.2 mm x 1.57 mmt
Board Size
114.3 mm x 76.2 mm x 1.6 mmt
2 Internal Layers
Copper Pattern
74.2 mm x 74.2 mm
Thickness
35 μm
Thermal Via
(Note 5)
Pitch
Diameter
1.20 mm
Φ0.30 mm
Bottom
Copper Pattern
74.2 mm x 74.2 mm
Thickness
70 μm
(Note 5)
This thermal via connects with the copper pattern of all layers.
Use a thermal design that has sufficient margin in consideration of power dissipation under actual operating conditions. This
IC exposes its frame at the backside of package. Note that this part is assumed to be used after providing heat dissipation
treatment to improve heat dissipation efficiency. Try to put heat dissipation pattern as wide as possible not only on the board
surface but also on the backside.
Under the insufficient heat dissipation and excessive large signal input condition, power dissipation (Pdiss) exceeds
maximum power dissipation (Pd) and thermal shutdown function may operate. Thermal design should be considered so that
Pdiss is lower than Pd. Reference data of Pdiss is listed on P.7.
(Tjmax : Maximum Junction Temperature = 150 °C, Ta : Operating Ambient Temperature[°C], θja : Package Thermal
Resistance[°C/W])
Power dissipation:
= ( − ) /
[W]
This IC has thermal shutdown function. Thermal shutdown operates when Tj (junction temperature, which is assumed to be
same as chip temperature) rises over about 180 °C (Typ) and be released when Tj fall about 160 °C (Typ) or less.
Thermal shutdown is designed to protect the IC from temperature condition that exceeds Tjmax = 150 °C, not to protect or
warrant application set.
Note that device reliability is affected if it is used under temperature thermal shutdown operates.
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BD783xxEFJ-M Series (Including products under development)
Recommended Operating Conditions
Parameter
Operating Supply Voltage
Operating Temperature
Load Resistance
Symbol
VDD
Topr
R
L
Min
4.0
-40
3.2
Typ
5.0
+25
8.0
Max
5.5
+105
38.4
Unit
V
°C
Ω
Caution:
Operating supply voltage and operating temperature are the ranges in which the IC is available for basic operation.
(Basic operation means that the IC operates without emitting unexpected noise or stopping signal.)
Characteristics and rating are not warranted in the whole operating supply voltage and operating temperature.
Electrical Characteristics 1
(Unless otherwise specified Ta = -40 °C to +105 °C, VDD = 5.0 V, f = 1 kHz, R
L
= 8 Ω, BTL
(Note 1)
, Active)
Parameter
Quiescent Current
Shutdown Current
Input Impedance
Output Offset Voltage
Control Pin (SDB)
Input Voltage
High Level
Low Level
Detection
Release
V
IH
V
IL
V
UVLO_DET
V
UVLO_REL
2.0
0
-
-
-
-
3.43
3.58
VDD
0.3
3.80
3.95
V
V
V
V
Symbol
I
CC
I
SD
Z
IN
V
OFS
Min
-
-
Z
IN
x0.4
-30
Limits
Typ
2.5
0.1
Z
IN
0
Max
6.0
25.0
Z
IN
x1.6
+30
Unit
mA
µA
kΩ
mV
Conditions
No load
Shutdown
SDB = Low
Refer to the table below
OUTP-OUTN
Under Voltage Lock Out (UVLO)
Threshold Supply
Voltage
(Note 1)
"BTL" means the state that R
L
is connected between the OUTP pin (pin5) and the OUTN pin (pin8).
Part Number
BD78306EFJ-M
BD78308EFJ-M
BD78310EFJ-M
BD78312EFJ-M
BD78314EFJ-M
BD78316EFJ-M
Z
IN
[
kΩ
]
(Typ)
45
40
35
30
25
20
Part Number
BD78318EFJ-M
BD78320EFJ-M
BD78322EFJ-M
BD78324EFJ-M
BD78326EFJ-M
-
Z
IN
[
kΩ
]
(Typ)
18
15
12
10
8
-
Electrical Characteristics 2
(Unless otherwise specified Ta = 25 °C, VDD = 5.0 V, f = 1 kHz, R
L
= 8 Ω, BTL, Active)
Parameter
Rated Output Power
(Note 2)
Symbol
P
O
Min
0.9
Limits
Typ
1.2
Max
1.6
Unit
W
Conditions
THD+N = 1 %,
BW = 400 Hz to 30 kHz
Continuous output time
60 s
THD+N = 10 %,
BW = 400 Hz to 30 kHz
Continuous output time
90 s
P
O
= 1 W
BW = 400 Hz to 30 kHz
P
O
= 0.5 W
G
V
= 6 dB to 26 dB
Vin = 0.1 V
RMS
BW = 400 Hz to 30 kHz
Vripple = 0.2 V
P-P
, C
1
= 0.47 µF
BW = A-Weight
C
1
= 0.47 µF
BW = A-Weight
Maximum Output Power
Total Harmonic Distortion + Noise
Voltage Gain
(Note 2)
Shutdown Attenuation
Power Supply Rejection Ratio
Output Noise Voltage
P
OMAX
THD+N
G
V
ATT
SD
PSRR
V
NO
-
-
G
V
- 1
-
-
-
1.6
-
G
V
-90
-60
-
-
0.5
G
V
+ 1
-80
-40
100
W
%
dB
dB
dB
µV
RMS
(Note 2)
The typical performance of device is shown Output Power and Voltage Gain. It largely depends on the board layout, parts, and power supply. The typical
values are measured with the device and parts mounting on surface of ROHM’s board directly and soldering thermal pad backside of package to top
layer cupper pattern of the board.
This IC is applicable to only dynamic speaker, not to other loads.
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BD783xxEFJ-M Series (Including products under development)
Typical Performance Curves
2.0
R
L
= No Load
R
L
= 8 Ω
SDB = 0 V
4.0
Quiescent Current : I
CC
[mA]
Shutdown Current : I
SD
[µA]
3.0
V
UVLO_DET
1.5
2.0
1.0
1.0
V
UVLO_REL
0.5
0.0
3
4
5
6
7
Supply Voltage : VDD [V]
Figure 3. Quiescent Current vs Supply Voltage
0.0
0
1
2
3
4
5
6
7
Supply Voltage : VDD [V]
Figure 4. Shutdown Current vs Supply Voltage
Total Harmonic Distortion + Noise : THD+N [%]
Total Harmonic Distortion + Noise : THD+N [%]
BD78306EFJ-M
10
VDD = 5 V
R
L
= 8 Ω
BD78326EFJ-M
10
1
1
0.1
0.1
VDD = 5 V
R
L
= 8 Ω
0.01
f = 100 Hz (30 kHz LPF)
f = 1 kHz (BW = 400 Hz to 30 kHz)
f = 10 kHz (BW = 400 Hz to 80 kHz)
0.001
0.001
0.01
0.1
1
10
0.01
f = 100 Hz (30 kHz LPF)
f = 1 kHz (BW = 400 Hz to 30 kHz)
f = 10 kHz (BW = 400 Hz to 80 kHz)
0.001
0.001
0.01
0.1
1
10
Output Power : P
O
[W]
Figure 5. Total Harmonic Distortion + Noise vs Output Power
Output Power : P
O
[W]
Figure 6. Total Harmonic Distortion + Noise vs Output Power
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19.Jul.2019 Rev.001