2SJ198 datasheet, PDF - EEWORLD Datasheet

2SJ198: DescriptionSmall Signal Field-Effect Transistor, 0.5A I(D), 100V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET; CategoryDiscrete semiconductor The transistor; File Size341KB，6 Pages; ManufacturerNEC Electronics

Download Datasheet Parametric View All

2SJ198 Overview

Small Signal Field-Effect Transistor, 0.5A I(D), 100V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	NEC Electronics
package instruction	CYLINDRICAL, O-PBCY-T3
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	GATE PROTECTED
Configuration	SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage	100 V
Maximum drain current (ID)	0.5 A
Maximum drain-source on-resistance	2.5 Ω
FET technology	METAL-OXIDE SEMICONDUCTOR
JESD-30 code	O-PBCY-T3
JESD-609 code	e0
Number of components	1
Number of terminals	3
Operating mode	ENHANCEMENT MODE
Package body material	PLASTIC/EPOXY
Package shape	ROUND
Package form	CYLINDRICAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Polarity/channel type	P-CHANNEL
Certification status	Not Qualified
surface mount	NO
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
transistor applications	SWITCHING
Transistor component materials	SILICON
Base Number Matches	1

How to evaluate the low power consumption of FPGA?: Recently, everyone is analyzing the data on FPGA low power consumption.I'll join in the fun,Let’s discuss with you how to define low power consumption of FPGA.To be honest, I didn’t pay much attention...; wstt FPGA/CPLD

Analysis of the "Signal" topic in the National College Student Electronics Contest: 1. Previous " Signal Source " Competition Topics In the 11th National Undergraduate Electronic Design Competition, there were only five signal source questions [ 1] : ①Signal Generator (8th session , ...; 宋元浩 Electronics Design Contest

Matlab Lesson 4 - Polynomial Arrays: Setting ranges and drawing! [[i] This post was last edited by gaoxiao on 2009-6-12 14:20 [/i]]...; gaoxiao Microcontroller MCU

Xilinx clock management: Hello everyone! How do you manage the clock in ise?...; applelonger FPGA/CPLD

Find the right solution: Hello everyone, I am looking for an ARM solution, Ubuntu system, CPU can be 6410 or other, need a full set of information, preferably a ready-made solution, which can be used with a little modificatio...; tryagain1 Linux and Android

I have just started learning Cadence Virtuoso and found that as long as the schematic diagram appears in the parallel inductor simulation, an error will be reported.: I have just started learning Cadence Virtuoso, and I found that whenever there is a parallel inductor simulation in the schematic diagram, it will report an error that the parallel inductor forms a sh...; 非标准理工男 Analog electronics

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components