Features
•
Low-voltage Operation
– 1.8V (V
CC
= 1.8V to 3.6V)
– 2.5V (V
CC
= 2.5V to 5.5V)
Internally Organized 131,072 x 8
Two-wire Serial Interface
Schmitt Triggers, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
400 kHz (1.8V) and 1 MHz (5V, 2.5V) Clock Rate
Write Protect Pin for Hardware and Software Data Protection
256-byte Page Write Mode (Partial Page Writes Allowed)
Random and Sequential Read Modes
Self-timed Write Cycle (5 ms Typical)
High Reliability
– Endurance: 1,000,000 Write Cycles/Page
– Data Retention: 40 Years
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-lead Ultra Thin
Small Array (SAP), and 8-ball dBGA2 Packages
Die Sales: Wafer Form, Tape and Reel and Bumped Die
•
•
•
•
•
•
•
•
•
•
Two-wire Serial
EEPROM
1M (131,072 x 8)
•
•
Description
The AT24C1024B provides 1,048,576 bits of serial electrically erasable and program-
mable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The
device’s cascadable feature allows up to four devices to share a common two-wire
bus. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available
in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP,
8-ball dBGA2 and 8-lead Ultra Thin SAP packages. In addition, the entire family is
available in 1.8V (1.8V to 3.6V) and 2.5V (2.5V to 5.5V) versions.
8-lead PDIP
8-lead SOIC
NC
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
AT24C1024B
with Two Device
Address Inputs
NC
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
8-lead TSSOP
NC
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
8-lead dBGA2
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
NC
A1
A2
GND
8-lead Ultra-Thin SAP
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
Bottom View
NC
A1
A2
GND
Rev. 5194F–SEEPR–1/08
Bottom View
Table 0-1.
Pin Name
A1
A2
SDA
SCL
WP
NC
Pin Configurations
Function
Address Input
Address Input
Serial Data
Serial Clock Input
Write Protect
No Connect
1. Absolute Maximum Ratings*
Operating Temperature..................................–55 C to +125 C
Storage Temperature .....................................–65 C to +150 C
Voltage on Any Pin
with Respect to Ground .................................... –1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
2
AT24C1024B
5194F–SEEPR–1/08
AT24C1024B
Figure 1-1.
Block Diagram
VCC
GND
WP
SCL
SDA
START
STOP
LOGIC
LOAD
DEVICE
ADDRESS
COMPARATOR
A
2
A
1
A
0
R/W
COMP
SERIAL
CONTROL
LOGIC
EN
H.V. PUMP/TIMING
DATA RECOVERY
INC
X DEC
LOAD
DATA WORD
ADDR/COUNTER
EEPROM
Y DEC
SERIAL MUX
D
IN
D
OUT
D
OUT
/ACK
LOGIC
2. Pin Description
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each EEPROM
device and negative edge clock data out of each device.
SERIAL DATA (SDA):
The SDA pin is bi-directional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open-collector
devices.
DEVICE/ADDRESSES (A1/A2):
The A1, A2 pin is a device address input that can be hardwired
or left not connected for hardware compatibility with other AT24Cxx devices. When the A1, A2
pins are hardwired, as many as four 1024K devices may be addressed on a single bus system
(device addressing is discussed in detail under the Device Addressing section). If the A1/A2 pins
are left floating, the A1/A2 pin will be internally pulled down to GND if the capacitive coupling to
the circuit board V
CC
plane is <3 pF. If coupling is >3 pF, Atmel recommends connecting the
A1/A2 pin to GND.
WRITE PROTECT (WP):
The write protect input, when connected to GND, allows normal write
operations. When WP is connected high to V
CC
, all write operations to the memory are inhibited.
If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive cou-
pling to the circuit board V
CC
plane is <3 pF. If coupling is >3 pF, Atmel recommends connecting
the pin to GND. Switching WP to V
CC
prior to a write operation creates a software write-protect
function.
3
5194F–SEEPR–1/08
3. Memory Organization
AT24C1024B, 1024K SERIAL EEPROM:
The 1024K is internally organized as 512 pages of
256 bytes each. Random word addressing requires a 17-bit data word address.
Table 3-1.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25 C, f = 1.0 MHz, V
CC
= +1.8V
Symbol
C
I/O
C
IN
Note:
Test Condition
Input/Output Capacitance (SDA)
Input Capacitance (A
1
, SCL)
1. This parameter is characterized and is not 100% tested.
Max
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
Table 3-2.
DC Characteristics
Applicable over recommended operating range from: T
AI
= –40 C to +85 C, V
CC
= +1.8V to +5.5V (unless otherwise noted)
Symbol
V
CC1
V
CC2
I
CC
I
CC
I
SB1
Parameter
Supply Voltage
Supply Voltage
Supply Current
Supply Current
Standby Current
V
CC
= 5.0V
V
CC
= 5.0V
V
CC
= 1.8V
V
CC
= 3.6V
Standby Current
Input Leakage Current
Output Leakage
Current
Input Low Level
(1)
Input High Level
(1)
Output Low Level
Output Low Level
V
CC
= 1.8V
V
CC
= 3.0V
I
OL
= 0.15 mA
I
OL
= 2.1 mA
V
CC
= 2.5V
V
CC
= 5.5V
V
IN
= V
CC
or V
SS
V
OUT
= V
CC
or V
SS
–0.6
V
CC
x 0.7
READ at 400 kHz
WRITE at 400 kHz
V
IN
= V
CC
or V
SS
Test Condition
Min
1.8
2.5
Typ
Max
3.6
5.5
2.0
3.0
1.0
3.0
2.0
V
IN
= V
CC
or V
SS
0.10
0.05
6.0
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.2
0.4
Units
V
V
mA
mA
A
A
A
A
A
A
V
V
V
V
I
SB2
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Note:
1. V
IL
min and V
IH
max are reference only and are not tested.
Table 3-3.
AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from T
AI
= 40 C to +85 C, V
CC
= +1.8V to +3.6V, CL = 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
1.8-volt
Symbol
f
SCL
t
LOW
t
HIGH
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
1.3
0.6
Min
Max
400
0.4
0.4
2.5, 5.0-volt
Min
Max
1000
Units
kHz
s
s
4
AT24C1024B
5194F–SEEPR–1/08
AT24C1024B
Table 3-3.
AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from T
AI
= 40 C to +85 C, V
CC
= +1.8V to +3.6V, CL = 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
1.8-volt
Symbol
t
i
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
(1)
Notes:
Parameter
Noise Suppression Time
(1)
Clock Low to Data Out Valid
Time the bus must be free before a
new transmission can start
(1)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time
(1)
Inputs Fall Time
(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
25°C, Page Mode, 3.3V
0.6
50
5
1,000,000
0.05
1.3
0.6
0.6
0
100
0.3
300
0.25
50
5
Min
Max
100
0.9
0.05
0.5
0.25
0.25
0
100
0.3
100
2.5, 5.0-volt
Min
Max
50
0.55
Units
ns
s
s
s
s
s
ns
s
ns
s
ns
ms
Write
Cycles
1. This parameter is ensured by characterization only.
2. AC measurement conditions:
R
L
(connects to V
CC
): 1.3 k (2.5V, 5V), 10 k (1.8V)
Input pulse voltages: 0.3 V
CC
to 0.7 V
CC
Input rise and fall times: 50 ns
Input and output timing reference voltages: 0.5 V
CC
4. Device Operation
CLOCK and DATA TRANSITIONS:
The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (see
Figure 4-4 on
page 7).
Data changes during SCL high periods will indicate a start or stop condition as defined
below.
5
5194F–SEEPR–1/08
京公网安备 11010802033920号
EEWORLD
