module test;
reg [14*8:1] str_v;
initial
begin
str_v="hello";
$display ("%s is stored as %h",str_v,str_v);
str_v={str_v,"!!!"};
$display ("%s is stored as %h",str_v,str_v);
end
endmodule
After enterin...
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FPGA/CPLD
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