LFE3-70E-7FN1156I datasheet, PDF

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LFE3-70E-7FN1156I: Descriptionfpga - field programmable gate array 66.5K luts, 490 I/O 7 speed; CategoryProgrammable logic devices Programmable logic; File Size3MB，130 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com; Environmental Compliance

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LFE3-70E-7FN1156I Overview

fpga - field programmable gate array 66.5K luts, 490 I/O 7 speed

LFE3-70E-7FN1156I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Lattice
Parts packaging code	BGA
package instruction	BGA, BGA1156,34X34,40
Contacts	1156
Reach Compliance Code	not_compliant
ECCN code	EAR99
maximum clock frequency	420 MHz
JESD-30 code	S-PBGA-B1156
JESD-609 code	e1
length	35 mm
Humidity sensitivity level	3
Number of entries	490
Number of logical units	67000
Output times	490
Number of terminals	1156
Maximum operating temperature	100 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA1156,34X34,40
Package shape	SQUARE
Package form	GRID ARRAY
power supply	1.2 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	2.6 mm
Maximum supply voltage	1.26 V
Minimum supply voltage	1.14 V
Nominal supply voltage	1.2 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	35 mm

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LatticeECP3 Family Data Sheet

Preliminary DS1021 Version 01.6, March 2010

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Lattice Semiconductor

Introduction

LatticeECP3 Family Data Sheet

Introduction

The LatticeECP3™ (EConomy Plus Third generation) family of FPGA devices is optimized to deliver high perfor-

mance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous

interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture

and the use of 65nm technology making the devices suitable for high-volume, high-speed, low-cost applications.

The LatticeECP3 device family expands look-up-table (LUT) capacity to 149K logic elements and supports up to

486 user I/Os. The LatticeECP3 device family also offers up to 320 18x18 multipliers and a wide range of parallel

I/O standards.

The pre-engineered source synchronous logic implemented in the LatticeECP3 device family supports a broad

range of interface standards, including DDR3, XGMII and 7:1 LVDS.

The LatticeECP3 device family also features high speed SERDES with dedicated PCS functions. High jitter toler-

ance and low transmit jitter allow the SERDES plus PCS blocks to be configured to support an array of popular

data protocols including PCI Express, SMPTE, Ethernet (XAUI, GbE, and SGMII) and CPRI. Transmit Pre-empha-

sis and Receive Equalization settings make the SERDES suitable for transmission and reception over various

forms of media.

The LatticeECP3 devices also provide flexible, reliable and secure configuration options, such as dual-boot capa-

bility, bit-stream encryption, and TransFR field upgrade features.

The ispLEVER

design tool suite from Lattice allows large complex designs to be efficiently implemented using the

LatticeECP3 FPGA family. Synthesis library support for LatticeECP3 is available for popular logic synthesis tools.

The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place

and route the design in the LatticeECP3 device. The ispLEVER tool extracts the timing from the routing and back-

annotates it into the design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP3

family. By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the

unique aspects of their design, increasing their productivity.

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1-2

The LatticeECP3 FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP3 devices

utilize reconfigurable SRAM logic technology and provide popular building blocks such as LUT-based logic, distrib-

uted and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source

synchronous I/O support, enhanced sysDSP slices and advanced configuration support, including encryption and

dual-boot capabilities.

LatticeECP3 Family Data Sheet

Architecture

March 2010

Preliminary Data Sheet DS1021

Architecture Overview

Each LatticeECP3 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-

spersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sys-

DSP™ Digital Signal Processing slices, as shown in Figure 2-1. In addition, the LatticeECP3 family contains

SERDES Quads on the bottom of the device.

There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional Unit

without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF

block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for

flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-

dimensional array. Only one type of block is used per row.

The LatticeECP3 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large, dedicated

18Kbit fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths as RAM or

ROM. In addition, LatticeECP3 devices contain up to two rows of DSP slices. Each DSP slice has multipliers and

adder/accumulators, which are the building blocks for complex signal processing capabilities.

The LatticeECP3 devices feature up to 16 embedded 3.2Gbps SERDES (Serializer / Deserializer) channels. Each

SERDES channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic. Each

group of four SERDES channels, along with its Physical Coding Sub-layer (PCS) block, creates a quad. The func-

tionality of the SERDES/PCS quads can be controlled by memory cells set during device configuration or by regis-

ters that are addressable during device operation. The registers in every quad can be programmed via the

SERDES Client Interface (SCI). These quads (up to four) are located at the bottom of the devices.

Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the

LatticeECP3 devices are arranged in seven banks, allowing the implementation of a wide variety of I/O standards.

In addition, a separate I/O bank is provided for the programming interfaces. 50% of the PIO pairs on the left and

right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic also includes pre-engi-

neered support to aid in the implementation of high speed source synchronous standards such as XGMII, 7:1

LVDS, along with memory interfaces including DDR3.

Other blocks provided include PLLs, DLLs and configuration functions. The LatticeECP3 architecture provides two

Delay Locked Loops (DLLs) and up to ten Phase Locked Loops (PLLs). In addition, each LatticeECP3 family mem-

ber provides two DLLs per device. The PLL and DLL blocks are located at the end of the EBR/DSP rows.

The configuration block that supports features such as configuration bit-stream decryption, transparent updates

and dual-boot support is located toward the center of this EBR row. Every device in the LatticeECP3 family sup-

ports a sysCONFIG™ port located in the corner between banks one and two, which allows for serial or parallel

device configuration.

In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator and soft error

detect capability. The LatticeECP3 devices use 1.2V as their core voltage.

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

www.latticesemi.com

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2-1

DS1021

Architecture_01.5

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