Si5375B-A-BL datasheet, PDF - EEWORLD Datasheet

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Si5375B-A-BL: Descriptionclock synthesizer / jitter cleaner loop BW 60hz-8.4 khz 4in/out 2khz-808mhz; Categorysemiconductor Other integrated circuit (IC); File Size269KB，54 Pages; ManufacturerSilicon; Environmental Compliance

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Si5375B-A-BL Overview

clock synthesizer / jitter cleaner loop BW 60hz-8.4 khz 4in/out 2khz-808mhz

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Si5375

4-PLL A

- F

REQUENCY

RECISION

LOCK

ULTIPLIER

I T T E R

TTENUA TOR

Features



Highly integrated, 4–PLL clock



multiplier/jitter attenuator

Four independent DSPLLs

support any-frequency synthesis



and jitter attenuation

Four inputs/four outputs



Each DSPLL can generate any



frequency from 2 kHz to

808 MHz from a 2 kHz to

710 MHz input

Ultra-low jitter clock outputs:



350 fs rms (12 kHz– 20 MHz)



and 410 fs rms (50 kHz–80 MHz)



typical

Meets ITU-T G.8251 and

Telcordia GR-253-CORE OC-192



jitter specifications

Integrated loop filter with

programmable bandwidth as low

as 60 Hz

Simultaneous free-run and

synchronous operation

Automatic/manual hitless input

clock switching

Selectable output clock signal

format (LVPECL, LVDS, CML,

CMOS)

LOL and interrupt alarm outputs

C programmable

Single 1.8 V ±5% or 2.5 V ±10%

operation with high PSRR on-

chip voltage regulator

10x10 mm PBGA

Ordering Information:

See page 48.

Applications



High density any-port, any-

protocol, any-frequency line

cards



ITU-T G.709 OTN custom FEC



10/40/100G



OC-48/192, STM-16/64



1/2/4/8/10G Fibre Channel



GbE/10GbE Synchronous Ethernet



Carrier Ethernet, multi-service

switches and routers



MSPP, ROADM, P-OTS,

muxponders

Description

The Si5375 is a highly-integrated, 4-PLL, jitter-attenuating precision clock

multiplier for applications requiring sub 1 ps jitter performance. Each of the

DSPLL

clock multiplier engines accepts an input clock ranging from 2 kHz to

710 MHz and generates an output clock ranging from 2 kHz to 808 MHz. The

device provides virtually any frequency translation combination across this

operating range. For asynchronous, free-running clock generation

applications, the Si5375’s reference oscillator can be used as a clock source

for any of the four DSPLLs. The Si5375 input clock frequency and clock

multiplication ratio are programmable through an I

C interface. The Si5375 is

based on Silicon Laboratories' third-generation DSPLL

technology, which

provides any-frequency synthesis and jitter attenuation in a highly-integrated

PLL solution that eliminates the need for external VCXO and loop filter

components. Each DSPLL loop bandwidth is digitally-programmable,

providing jitter performance optimization at the application level. The device

operates from a single 1.8 or 2.5 V supply with on-chip voltage regulators with

excellent PSRR. The Si5375 is ideal for providing clock multiplication and

jitter attenuation in high port count optical line cards requiring independent

timing domains.

Rev. 1.0 8/12

Si5375

Si5375

ABLE

Section

ONTENTS

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3. Typical Phase Noise Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5. Si5375 Application Examples and Suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

5.1. Schematic and PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.2. Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.3. SCL Leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.4. RSTL_x Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.5. Reference Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.6. Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.7. OSC_P and OSC_N Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

7.1. ICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8. Pin Descriptions: Si5375 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

11. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

12. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12.1. Si5375 Top Marking (PBGA, Lead-Free) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12.2. Top Marking Explanation (PBGA, Lead-Free) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12.3. Si5375 Top Marking (PBGA, Lead-Finish) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

12.4. Top Marking Explanation (PBGA, Lead-Finish) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Rev. 1.0

Si5375B-A-BL Related Products

	Si5375B-A-BL	Si5375
Description	clock synthesizer / jitter cleaner loop BW 60hz-8.4 khz 4in/out 2khz-808mhz	the si5375 is a highly-integrated, 4-pll, jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance

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