DS12B887
DS12B887
Real Time Clock
FEATURES
PIN ASSIGNMENT
NC
NC
NC
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
SQW
NC
RCLR
NC
IRQ
NC
DS
NC
R/W
AS
CS
•
Drop-in replacement for IBM AT computer clock/cal-
endar
•
Pin compatible with the MC146818B and DS1287
•
Totally nonvolatile with over 10 years of operation in
the absence of power
•
Self-contained
•
Counts
subsystem includes lithium, quartz,
and support circuitry
seconds, minutes, hours, days, day of the
week, date, month, and year with leap year com-
pensation
alarm
•
Binary or BCD representation of time, calendar, and
•
12- or 24-hour clock with AM and PM in 12-hour mode
•
Daylight Savings Time option
•
Multiplex bus for pin efficiency
•
Interfaced with software as 128 RAM locations
– 14 bytes of clock and control registers
– 114 bytes of general purpose RAM
24 PIN ENCAPSULATED PACKAGE
PIN DESCRIPTION
AD0-AD7
NC
CS
AS
R/W
DS
IRQ
SQW
V
CC
GND
RCLR
–
–
–
–
–
–
–
–
–
–
–
Multiplexed Address/Data Bus
No Connection
Chip Select
Address Strobe
Read/Write Input
Data Strobe
Interrupt Request Output
Square Wave Output
+5 Volt Supply
Ground
RAM Clear
•
Programmable square wave output signal
•
Bus-compatible interrupt signals (IRQ)
•
Three
interrupts are separately software-maskable
and testable
– Time-of-day alarm once/second to once/day
– Periodic rates from 122
µs
to 500 ms
– End of clock update cycle
DESCRIPTION
The DS12B887 Real Time Clock plus RAM is designed
to be a direct replacement for the DS1287A or
DS12887A. The DS12B887 is identical in form, fit, and
function to the DS1287A or DS12887A, with the excep-
tion of RCLR, and has an additional 64 bytes of general
purpose RAM. Access to this additional RAM space is
determined by the logic level presented on AD6 during
the address portion of an access cycle. A lithium energy
source, quartz crystal, and write-protection circuitry are
contained within a 24-pin dual in-line package. As such,
the DS12B887 is a complete subsystem replacing 16
components in a typical application. The functions
include a nonvolatile time-of-day clock, an alarm, a one-
hundred-year calendar, programmable interrupt,
square wave generator, and 114 bytes of nonvolatile
static RAM. The real time clock is distinctive in that
time-of-day and memory are maintained even in the
absence of power.
ECopyright
1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
080895 1/16
DS12B887
OPERATION
The block diagram in Figure 1 shows the pin connec-
tions with the major internal functions of the DS12B887.
The following paragraphs describe the function of each
pin.
BLOCK DIAGRAM DS12B887
Figure 1
OSC.
B8
B64
B64
CS
V
CC
V
BAT
POWER
SWITCH
AND
WRITE
PROTECT
V
CC
POK
PERIODIC INTERRUPT/SQUARE WAVE
SELECTOR
SQUARE
WAVE OUT
CS
SQW
IRQ
REGISTERS A,B,C,D
DS
R/W
AS
ADO–
AD7
BCD/
BINARY
INCREMENT
USER RAM
114 BYTES
RAM
CLEAR
LOGIC
RCLR
BUS
INTERFACE
DOUBLE
BUFFERED
CLOCK/
CALENDAR
UPDATE
CLOCK, CALENDAR,
AND ALARM RAM
POWER-DOWN/POWER-UP
CONSIDERATIONS
The Real Time Clock function will continue to operate
and all of the RAM, time, calendar, and alarm memory
locations remain nonvolatile regardless of the level of
the V
CC
input. When V
CC
is applied to the DS12B887
and reaches a level of greater than 4.25 volts, the device
becomes accessible after 200 ms, provided that the
oscillator is running and the oscillator countdown chain
is not in reset (see Register A). This time period allows
the system to stabilize after power is applied. When
V
CC
falls below 4.25 volts, the chip select input is inter-
nally forced to an inactive level regardless of the value of
CS at the input pin. The DS12B887 is, therefore, write-
protected. When the DS12B887 is in a write-protected
state, all inputs are ignored and all outputs are in a high
impedance state. When V
CC
falls below a level of
approximately 3 volts, the external V
CC
supply is
switched off and an internal lithium energy source sup-
plies power to the Real Time Clock and the RAM
memory.
080895 2/16
DS12B887
SIGNAL DESCRIPTIONS
GND, V
CC
- DC power is provided to the device on these
pins. V
CC
is the +5 volt input. When 5 volts are applied
within normal limits, the device is fully accessible and
data can be written and read. When V
CC
is below 4.25
volts typical, reads and writes are inhibited. However,
the timekeeping function continues unaffected by the
lower input voltage. As V
CC
falls below 3 volts typical,
the RAM and timekeeper are switched over to an inter-
nal lithium energy source. The timekeeping function
maintains an accuracy of
±1
minute per month at 25
o
C
regardless of the voltage input on the V
CC
pin.
SQW (Square Wave Output) - The SQW pin can output
a signal from one of 13 taps provided by the 15 internal
divider stages of the Real Time Clock. The frequency of
the SQW pin can be changed by programming Register
A as shown in Table 1. The SQW signal can be turned
on and off using the SQWE bit in Register B. The SQW
signal is not available when V
CC
is less than 4.25 volts
typical.
PERIODIC INTERRUPT RATE AND SQUARE WAVE OUTPUT FREQUENCY
Table 1
SELECT BITS REGISTER A
RS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
RS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
RS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
RS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
t
PI
PERIODIC
INTERRUPT RATE
None
3.90625 ms
7.8125 ms
122.070
ms
244.141
ms
488.281
ms
976.5625
ms
1.953125 ms
3.90625 ms
7.8125 ms
15.625 ms
31.25 ms
62.5 ms
125 ms
250 ms
500 ms
SQW OUTPUT
FREQUENCY
None
256 Hz
128 Hz
8.192 kHz
4.096 kHz
2.048 kHz
1.024 kHz
512 Hz
256 Hz
128 Hz
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
080895 3/16
DS12B887
AD0-AD7 (Multiplexed Bidirectional Address/Data
Bus)
- Multiplexed buses save pins because address
information and data information time share the same
signal paths. The addresses are present during the first
portion of the bus cycle and the same pins and signal
paths are used for data in the second portion of the cycle.
Address/data multiplexing does not slow the access time
of the DS12B887 since the bus change from address to
data occurs during the internal RAM access time.
Addresses must be valid prior to the falling edge of AS/
ALE, at which time the DS12B887 latches the address
from AD0 to AD6. Valid write data must be present and
held stable during the latter portion of the DS or WR
pulses. In a read cycle the DS12B887 outputs 8 bits of
data during the latter portion of the DS or RD pulses. The
read cycle is terminated and the bus returns to a high
impedance state as RD transitions high.
AS (Address Strobe Input)
- A positive going address
strobe pulse serves to demultiplex the bus. The falling
edge of AS/ALE causes the address to be latched within
the DS12B887.
DS (Data Strobe or Read Input)
- The DS pin is called
Read(RD). RD identifies the time period when the
DS12B887 drives the bus with read data. The RD signal
is the same definition as the Output Enable (OE) signal
on a typical memory.
R/W (Read/Write Input)-The
R/W signal is an active low
signal called WR. In this mode the R/W pin has the
same meaning as the Write Enable signal (WE) on
generic RAMs.
CS (Chip Select Input)
- The Chip Select signal must
be asserted low for a bus cycle in the DS12B887 to be
accessed. CS must be kept in the active state during
RD and WR. Bus cycles which take place without
asserting CS will latch addresses but no access will
occur. When V
CC
is below 4.25 volts, the DS12B887
internally inhibits access cycles by internally disabling
the CS input. This action protects both the real time
clock data and RAM data during power outages.
IRQ (Interrupt Request Output)
- The IRQ pin is an
active low output of the DS12B887 that can be used as an
interrupt input to a processor. The IRQ output remains
low as long as the status bit causing the interrupt is pres-
ent and the corresponding interrupt-enable bit is set. To
clear the IRQ pin the processor program normally reads
the C register.
When no interrupt conditions are present, the IRQ level is
in the high impedance state. Multiple interrupting devices
can be connected to an IRQ bus. The IRQ bus is an open
drain output and requires an external pull-up resistor.
RCLR (RAM Clear)
- The RCLR pin is used to clear (set
to logic 1) all 114 bytes of general-purpose RAM but
does not affect the RAM associated with the real time
clock. In order to clear the RAM, RCLR must be forced
to an input logic of (-0.3 to +0.8 volts) when V
CC
is ap-
plied. The RCLR function is designed to be used via hu-
man interface (shorting to ground manually or by switch)
and not to be driven with external buffers. This pin is in-
ternally pulled up. Do not use an external pull-up resistor
on this pin.
ADDRESS MAP
The address map of the DS12B887 is shown in Figure 2.
The address map consists of 114 bytes of user RAM, 10
bytes of RAM that contain the RTC time, calendar, and
alarm data, and four bytes which are used for control
and status. All 128 bytes can be directly written or read
except for the following:
1. Registers C and D are read-only.
2. Bit 7 of Register A is read-only.
3. The high order bit of the seconds byte is read-only.
The contents of four registers (A,B,C, and D) are
described in the “Registers” section.
080895 4/16
DS12B887
ADDRESS MAP DS12B887
Figure 2
0
14 BYTES
13
14
0D
0E
00
0
1
2
3
4
5
6
7
8
9
10
11
12
127
7F
13
SECONDS
SECONDS ALARM
MINUTES
MINUTES ALARM
HOURS
HOURS ALARM
DAY OF THE WEEK
DAY OF THE MONTH
MONTH
YEAR
REGISTER A
REGISTER B
REGISTER C
REGISTER D
BINARY OR BCD INPUTS
080895 5/16
TIME, CALENDAR AND ALARM LOCATIONS
The time and calendar information is obtained by read-
ing the appropriate memory bytes. The time, calendar,
and alarm are set or initialized by writing the appropriate
RAM bytes. The contents of the ten time, calendar, and
alarm bytes can be either Binary or Binary-Coded Deci-
mal (BCD) format. Before writing the internal time, cal-
endar, and alarm registers, the SET bit in Register B
should be written to a logic one to prevent updates from
occurring while access is being attempted. In addition
to writing the ten time, calendar, and alarm registers in a
selected format (binary or BCD), the data mode bit (DM)
of Register B must be set to the appropriate logic level.
All ten time, calendar, and alarm bytes must use the
same data mode. The set bit in Register B should be
cleared after the data mode bit has been written to allow
the real time clock to update the time and calendar
bytes. Once initialized, the real time clock makes all
updates in the selected mode. The data mode cannot
be changed without reinitializing the ten data bytes.
Table 2 shows the binary and BCD formats of the ten
time, calendar, and alarm locations. The 24-12 bit can-
not be changed without reinitializing the hour locations.
When the 12-hour format is selected, the high order bit
of the hours byte represents PM when it is a logic one.
The time, calendar, and alarm bytes are always acces-
sible because they are double buffered. Once per
second the ten bytes are advanced by one second and
checked for an alarm condition. If a read of the time and
calendar data occurs during an update, a problem exists
where seconds, minutes, hours, etc. may not correlate.
The probability of reading incorrect time and calendar
data is low. Several methods of avoiding any possible
incorrect time and calendar reads are covered later in
this text.
The three alarm bytes can be used in two ways. First,
when the alarm time is written in the appropriate hours,
minutes, and seconds alarm locations, the alarm inter-
rupt is initiated at the specified time each day if the alarm
enable bit is high . The second use condition is to insert
a “don’t care” state in one or more of the three alarm
bytes. The “don’t care” code is any hexadecimal value
from C0 to FF. The two most significant bits of each byte
set the “don’t care” condition when at logic 1. An alarm
will be generated each hour when the “don’t care” bits
are set in the hours byte. Similarly, an alarm is gener-
ated every minute with “don’t care” codes in the hours
and minute alarm bytes. The “don’t care” codes in all
three alarm bytes create an interrupt every second.
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