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54F280DM

Description
Parity Generator/Checker, F/FAST Series, 9-Bit, Complementary Output, TTL, CDIP14, CERAMIC, DIP-14
Categorylogic    logic   
File Size176KB,11 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric View All

54F280DM Overview

Parity Generator/Checker, F/FAST Series, 9-Bit, Complementary Output, TTL, CDIP14, CERAMIC, DIP-14

54F280DM Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeDIP
package instructionDIP, DIP14,.3
Contacts14
Reach Compliance Codeunknown
Other featuresODD/EVEN PARITY GENERATOR
seriesF/FAST
JESD-30 codeR-GDIP-T14
JESD-609 codee0
length19.43 mm
Load capacitance (CL)50 pF
Logic integrated circuit typePARITY GENERATOR/CHECKER
Number of digits9
Number of functions1
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityCOMPLEMENTARY
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDIP
Encapsulate equivalent codeDIP14,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)38 mA
propagation delay (tpd)21 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
Base Number Matches1
54F 74F280 9-Bit Parity Generator Checker
August 1995
54F 74F280
9-Bit Parity Generator Checker
General Description
The ’F280 is a high-speed parity generator checker that ac-
cepts nine bits of input data and detects whether an even or
an odd number of these inputs is HIGH If an even number
of inputs is HIGH the Sum Even output is HIGH If an odd
number is HIGH the Sum Even output is LOW The Sum
Odd output is the complement of the Sum Even output
Features
Y
Guaranteed 4000V minimum ESD protection
Commercial
74F280PC
Military
Package
Number
N14A
Package Description
14-Lead (0 300 Wide) Molded Dual-In-Line
14-Lead Ceramic Dual-In-Line
14-Lead (0 150 Wide) Molded Small Outline JEDEC
14-Lead (0 300 Wide) Molded Small Outline EIAJ
14-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
54F280DM (Note 2)
74F280SC (Note 1)
74F280SJ (Note 1)
54F280FM (Note 2)
54F280LM (Note 2)
J14A
M14A
M14D
W14B
E20A
Note 1
Devices also available in 13 reel Use suffix
e
SCX and SJX
Note 2
Military grade device with environmental and burn-in processing Use suffix
e
DMQB FMQB and LMQB
Logic Symbols
Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
TL F 9512–3
IEEE IEC
TL F 9512 – 1
TL F 9512 – 2
TL F 9512–5
TRI-STATE is a registered trademark of National Semiconductor Corporation
C
1995 National Semiconductor Corporation
TL F 9512
RRD-B30M115 Printed in U S A
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