PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83908-02
L
OW
S
KEW
, 1-
TO
-8
C
RYSTAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
F
EATURES
•
8 LVCMOS/LVTTL outputs (19Ω typical output impedance)
•
2 Crystal oscillator input pairs
1 LVCMOS/LVTTL clock input
•
Crystal input frequencry range: 10MHz - 40MHz
•
Output frequency: 200MHz (typical) CLK0
•
Output Skew: TBD
•
Part to Part Skew: TBD
• RMS phase jitter @ 25MHz (100Hz - 1MHz):
0.22ps (typical) V
DD
= V
DDO
= 3.3V
Offset
Noise Power
100Hz .............. -111.4 dBc/Hz
1kHz .............. -139.9 dBc/Hz
10kHz .............. -157.3 dBc/Hz
100kHz .............. -157.5 dBc/Hz
•
Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
•
0°C to 70°C ambient operating temperature
•
Industrial temperature available upon request
G
ENERAL
D
ESCRIPTION
The ICS83908-02 is a low skew, high performance
ICS
1-to-8 Crystal Oscillator/3.3V LVCMOS-to-3.3V
HiPerClockS™
LVCMOS fanout buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS83908-02 has
selectable single ended clock or two crystal-oscillator inputs.
There is an output enable to disable the outputs by placing them
into a high-impedance state.
Guaranteed output and part-to-part skew characteristics
make the ICS83908-02 ideal for those applications demanding
well defined performance and repeatability.
B
LOCK
D
IAGRAM
OE
CLK_SEL0
Pullup
Pulldown
P
IN
A
SSIGNMENT
V
DD
XTAL_IN0
XTAL_OUT0
V
DDO
Q0
Q1
GND
Q2
Q3
V
DDO
CLK_SEL0
CLK0
Q0
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
XTAL_IN1
XTAL_OUT1
V
DDO
Q7
Q6
GND
Q5
Q4
V
DDO
CLK_SEL1
OE
CLK_SEL1 Pulldown
XTAL_IN0
OSC
0 0
XTAL_OUT0
ICS83908-02
XTAL_IN1
OSC
0 1
8 LVCMOS Outputs
XTAL_OUT1
Q7
CLK0
Pulldown
24-Lead, 173-MIL TSSOP
4.4mm x 7.8mm x 0.92mm
body package
G Package
Top View
1 0
1 1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83908AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83908-02
L
OW
S
KEW
, 1-
TO
-8
C
RYSTAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
Type
Power
Input
Power
Output
Power
Description
Core supply pin.
Crystal oscillator interface. XTAL_IN0 is the input.
XTAL_OUT0 is the output.
Output supply pins.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 3
4, 10, 15, 21
5, 6, 8,
9, 16, 17,
19, 20
7, 18, 24
11,
14
12
Name
V
DD
XTAL_IN0,
XTAL_OUT0
V
DDO
Q0, Q1, Q2,
Q3, Q4, Q5,
Q6, Q7
GND
CLK_SEL0,
CLK_SEL1
CLK0
Power supply ground.
Clock select inputs. See Table 3, Input Reference Function Table.
Input Pulldown
LVCMOS / LVTTL interface levels.
Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable. When LOW, outputs are in HIGH impedance state.
13
OE
Input
Pullup
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL_IN1 is the input.
XTAL_OUT1,
22, 23
Input
XTAL_OUT1 is the output.
XTAL_IN1
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
V
DDO
= 3.465V
V
DDO
= 2.625V
V
DDO
= 2V
V
DDO
= 3.3V ± 5%
R
OUT
Output Impedance
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 0.2V
Test Conditions
Minimum
Typical
4
51
51
7
7
6
19
TBD
TBD
Maximum
Units
pF
kΩ
kΩ
pF
pF
pF
Ω
Ω
Ω
T
ABLE
3. I
NPUT
R
EFERENCE
F
UNCTION
T
ABLE
Control Inputs
CLK_SEL1
CLK_SEL0
0
0
0
1
1
1
0
1
Reference
XTAL0 (default)
XTAL1
CLK0
CLK0
83908AG-02
www.icst.com/products/hiperclocks.html
2
REV. A JULY 20, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83908-02
L
OW
S
KEW
, 1-
TO
-8
C
RYSTAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
70°C/W (0 mps)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
25
121
Maximum
3.465
3.465
Units
V
V
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
26
82
Maximum
3.465
2.625
Units
V
V
mA
mA
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
1.6
Typical
3.3
1.8
26
53
Maximum
3.465
2.0
Units
V
V
mA
mA
T
ABLE
4D. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
13
77
Maximum
2.625
2.625
Units
V
V
mA
mA
T
ABLE
4E. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
83908AG-02
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
1.6
Typical
2.5
1.8
13
51
Maximum
2.625
2.0
Units
V
V
mA
mA
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
3
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83908-02
L
OW
S
KEW
, 1-
TO
-8
C
RYSTAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
Test Conditions
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
CLK0,
CLK_SEL0:1
OE
CLK0,
CLK_SEL0:1
OE
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DDO
= 3.3V ± 5%; NOTE 1
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 0.2V; NOTE 1
V
DDO
= 3.3V ± 5%; NOTE 1
-5
-150
2.6
1.8
1. 5
0.5
0.5
0. 4
Minimum
2.0
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0. 7
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
V
T
ABLE
4F. LVCMOS/LVTTL DC C
HARACTERISTICS
,
T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
I
IL
Input Low Current
V
OH
Output HighVoltage
V
OL
Output Low Voltage
V
DDO
= 2.5V ± 5%; NOTE 1
V
DDO
= 1.8V ± 0.2V; NOTE 1
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation / cut
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
10
Test Conditions
Minimum
Typical Maximum
40
50
7
1
Units
MHz
Ω
pF
mW
Fundamental
83908AG-02
www.icst.com/products/hiperclocks.html
4
REV. A JULY 20, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83908-02
L
OW
S
KEW
, 1-
TO
-8
C
RYSTAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
Test Conditions
Minimum
10
20 0
2
TBD
TBD
25MHz, (100Hz - 1MHz)
20% to 80%
0.22
457
50
10
8
Typical
Maximum
40
Units
MHz
MHz
ns
ps
ps
ps
ps
%
ns
ns
T
ABLE
6A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
tp
LH
w/External
Output Frequency XTAL
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Par t-to-Par t Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 5
t
sk(o)
t
sk(pp)
t
jit(Ø)
t
R
/ t
F
odc
t
EN
Output Disable Time; NOTE 5
t
DIS
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
T
ABLE
6B. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
tp
LH
w/External
Output Frequency XTAL
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Par t-to-Par t Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 5
Test Conditions
Minimum
10
20 0
2.2
TBD
TBD
25MHz, (100Hz - 1MHz)
20% to 80%
0.21
463
50
10
8
Typical
Maximum
40
Units
MHz
MHz
ns
ps
ps
ps
ps
%
ns
ns
t
sk(o)
t
sk(pp)
t
jit(Ø)
t
R
/ t
F
odc
t
EN
Output Disable Time; NOTE 5
t
DIS
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
83908AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 20, 2005
5
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