IC42S32400
IC42S32400L
1M Words x 32 Bits x 4 Banks (128-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
· Concurrent auto precharge
· Clock rate:166/143/125 MHz
· Fully synchronous operation
· Internal pipelined architecture
· Four internal banks (1M x 32bit x 4bank)
· Programmable Mode
-CAS#Latency:2 or 3
-Burst Length:1,2,4,8,or full page
-Burst Type:interleaved or linear burst
-Burst-Read-Single-Write
· Burst stop function
· Individual byte controlled by DQM0-3
· Auto Refresh and Self Refresh
· 4096 refresh cycles/64ms
· Single +3.3V ±0.3V power supply
· Interface:LVTTL
· Package:400 x 875 mil,86 Pin TSOP-2,0.50mm Pin
Pitch and 11x13mm, 90 Ball BGA, Ball pitch 0.8mm
· Pb-free package is available.
DESCRIPTION
The
ICSI
IC42S32400 and IC42S32400L is a high-speed
CMOS configured as a quad 1M x 32 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal,CLK).
Each of the 1M x 32 bit banks is organized as 4096 rows
by 256 columns by 32 bits.Read and write accesses start
at a selected locations in a programmed sequence.
Accesses begin with the registration of a BankActive
command which is then followed by a Read or Write
command
The
ICSI
IC42S32400 and IC42S32400L provides for
programmable Read or Write burst lengths of 1,2,4,8,or
full page, with a burst termination operation. An auto
precharge function may be enable to provide a self-timed
row precharge that is initiated at the end of the burst
sequence.The refresh functions,either Auto or Self
Refresh are easy to use.
By having a programmable mode register,the system
can choose the most suitable modes to maximize its
performance.
These devices are well suited for applications requiring
high memory bandwidth.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR038-0C 02/01/2005
IC42S32400
IC42S32400L
PIN DESCRIPTIONS
Table 1.Pin Details of IC42S32400 and IC42S32400L
Symbol Type
Description
CLK
CKE
Input
Input
Clock:CLK
is driven by the system clock.All SDRAM input signals are sampled on the positive edge
of CLK.CLK also increments the internal burst counter and controls the output registers.
Clock Enable:CKE
activates(HIGH)and deactivates(LOW)the CLK signal.If CKE goes low syn-
chronously with clock(set-up and hold time same as other inputs),the internal clock is suspended
from the next clock cycle and the state of output and burst address is frozen as long as the CKE
remains low.When all banks are in the idle state,deactivating the clock controls the entry to the
Power Down and Self Refresh modes.CKE is synchronous except after the device enters Power
Down and Self Refresh modes,where CKE becomes asynchronous until exiting the same mode.
The input buffers,including CLK,are disabled during Power Down and Self Refresh modes,providing
low standby power.
Bank Select:BS0
and BS1 defines to which bank the BankActivate,Read,Write,or BankPrecharge
command is being applied.
Address Inputs:A0-A11
are sampled during the BankActivate command (row address A0-A11)and
Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select one
location in the respective bank.During a Precharge command,A10 is sampled to determine if all
banks are to be precharged (A10 =HIGH).
The address inputs also provide the op-code during a Mode Register Set .
BS0,BS1 Input
A0-A11 Input
CS#
Input
Chip Select:CS#enables
(sampled LOW)and disables (sampled HIGH)the command decoder.All
commands are masked when CS#is sampled HIGH.CS#provides for external bank selection on
systems with multiple banks.It is considered part of the command code.
Row Address Strobe:The
RAS#signal defines the operation commands in conjunction with the
CAS#and WE#signals and is latched at the positive edges of CLK.When RAS# and CS#are as-
serted “LOW”and CAS#is asserted “HIGH,”either the BankActivate command or the Precharge
command is selected by the WE#signal.When the WE#is asserted “HIGH,”the BankActivate com-
mand is selected and the bank designated by BS is turned on to the active state.When the WE#is
asserted “LOW,”the Precharge command is selected and the bank designated by BS is switched to
the idle state after the precharge operation.
Column Address Strobe:The
CAS#signal defines the operation commands in conjunction with the
RAS#and WE#signals and is latched at the positive edges of CLK. When RAS#is held “HIGH”and
CS#is asserted “LOW,”the column access is started by asserting CAS#”LOW.”Then,the Read or
Write command is selected by asserting WE# “LOW”or “HIGH.”
Write Enable:The
WE#signal defines the operation commands in conjunction with the RAS#and
CAS#signals and is latched at the positive edges of CLK.The WE#input is used to select the
BankActivate or Precharge command and Read or Write command.
Data Input/Output Mask:DQM0-DQM3
are byte specific,nonpersistent I/O buffer controls. The I/O
buffers are placed in a high-z state when DQM is sampled HIGH.Input data is masked when DQM
is sampled HIGH during a write cycle.Output data is masked (two-clock latency)when DQM is
sampled HIGH during a read cycle.DQM3 masks DQ31-DQ24,DQM2 masks DQ23-DQ16,DQM1
masks DQ15-DQ8,and DQM0 masks DQ7-DQ0.
RAS#
Input
CAS#
Input
WE#
Input
DQM0-3 Input
DQ0-31 Input/Output Data I/O:The
DQ0-31 input and output data are synchronized with the positive edges of
CLK.The I/Os are byte-maskable during Reads and Writes.
4
Integrated Circuit Solution Inc.
DR038-0C 02/01/2005
51mcu
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