Features
•
Reference Oscillator up to 15 MHz
•
Two Programmable 16-bit Dividers Adjustable from 2 to 65535
•
Fine Tuning Steps
– AM
≥
1 kHz
– FM
≥
2 kHz
•
Loop-push-pull Stage for AM/FM
•
High Signal/Noise Ratio
AM/FM PLL
with 1 Switch
Description
The U4289BM is an integrated circuit in BICMOS technology for frequency synthesiz-
ers. It performs all the functions of a PLL radio tuning system and is controlled by a
2-wire bus. The device is designed for all frequency synthesizer applications in radio
receivers, as well as for RDS (Radio Data System) applications.
U4289BM
Figure 1.
Block Diagram
14
Oscillator
OSCOUT
SCL
SDA
AS
15
2
3
4
Phase
detector
I
2
C bus
interface
Current
sources
9
10
N-divider
1
VDD
16
GND1
12
13
PDAMO
VA
R-divider
Switching
output
OSCIN
5
11
SWO1
PDAM
FMOSC
6
PDFMO
AMOSC
8
AM/FM
switch
7
GND2
PDFM
Rev. 4757A–AUDR–10/03
U4289BM
Functional
Description
The U4289BM is controlled via the 2-wire bus. One module address byte, two subad-
dress bytes and five data bytes enable programming.
The module address contains a programmable address bit A 1, which (along with
address select input AS, pin 4), enables the operation of two U4289BM devices in one
system. If bit A 1 is identical with the status of the address select input AS, the chip is
selected.
The subaddress determines which of the data bytes is transmitted first. If the subad-
dress of the R-divider is transmitted, the sequence of the next data bytes is DB 0
(Status), DB 1 and DB 2. If the subaddress of the N-divider is transmitted, the sequence
of the next data bytes is DB 3 and DB 4. The bit organization of the module address,
subaddress and 5 data bytes is shown in table “Bit Organization” on page 7.
Each transmission on the bus begins with the “START” condition and has to be ended
by the “STOP” condition (see table “Transmission Protocol” on page 7).
The integrated circuit U4289BM has two separate inputs for the AM and FM oscillators.
Pre-amplified AM and FM signals are fed to the 16-bit R-divider via the AM/FM switch.
The AM/FM switch is software controlled. Tuning steps can be selected by the 16-bit
R-divider.
Furthermore, the device provides a digital memory phase detector and two separate
current sources for AM and FM amplifier (charge pump) as given in the Table “Electrical
Characteristics” on page 4. It allows independent gain adjustment, providing high cur-
rent for high-speed tuning and low current for stable tuning.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Supply voltage
Input voltage
Output current
Output drain voltage
Analog supply voltage with 220
Ω
serial
resistance 2 minutes
(1)
Output current
Ambient temperature range
Storage temperature range
Junction temperature
Electrostatic handling
(modified MIL STD 883 D method 3015.7: all
supply pins connected together)
Note:
1. Corresponding to the application circuit (Figure 8 on page 8)
Pins
1
2, 3, 4, 6, 8, 14,
15
3, 5
5
13
9, 12
Symbol
V
DD
V
I
I
O
V
OD
V
A
V
A
I
AO
T
amb
T
stg
T
j
±V
ESD
Value
-0.3 to +6
-0.3 to V
DD
+0.3
-1 to +5
15
6 to 15
24
-1 to +20
-30 to +85
-40 to +125
125
1000
Unit
V
V
mA
V
V
V
mA
°
C
°
C
°
C
V
Thermal Resistance
Parameters
Junction ambient
Symbol
R
thJA
Value
160
Unit
K/W
3
4757A–AUDR–10/03
Electrical Characteristics
V
DD
= 5 V, V
A
= 10 V, T
amb
= 25
°
C, unless otherwise specified
Parameters
Supply voltage
Quiescent supply current
FM input sensitivity,
R
G
= 50
Ω,
FMOSC
AM input sensitivity,
R
G
= 50
Ω,
AMOSC
Oscillator input sensitivity,
R
G
= 50
Ω,
OSCIN
Phase Detector PDFM
Output current 1
Output current 2
Leakage current
Phase Detector PDAM
Output current 1
Output current 2
Leakage current
Analog Output PDFMO, PDAMO
Saturation voltage LOW
Saturation voltage HIGH
Bus SCL, SDA, AS
Input voltage HIGH
Input voltage LOW
Output voltage acknowledge LOW
Clock frequency
Rise time SDA, SCL
Fall time SDA, SCL
Period of SCL HIGH
Period of SCL LOW
I
SDA
= 3 mA
2, 3, 4
2, 3, 4
3
2
2, 3
2, 3
2
2
V
iBUS
V
iBUS
V
O
f
SCL
t
r
t
f
t
H
t
L
4.0
4.7
3.0
0
V
DD
1.5
0.4
100
1
300
V
V
V
kHz
µs
ns
µs
µs
I = 15 mA
I = 15 mA
9, 12
9, 12
V
satL
V
satH
9.5
200
9.95
400
mW
V
11
11
11
±I
PDAM
±I
PDAM
±I
PDAML
160
40
200
50
240
60
20
µA
µA
µA
10
10
10
±I
PDFM
±I
PDFM
±I
PDFML
1600
400
2000
500
2400
600
20
µA
µA
nA
AM mode/FM mode
f
i
= 70 to 120 MHz
f
i
= 160 MHz
f
i
= 0.6 to 35 MHz
f
i
= 0.1 to 15 MHz
Test Conditions
Pins
1
1
6
6
8
14
Symbol
V
DD
I
DD
V
SFM
V
SFM
V
SAM
V
SOSC
40
150
40
100
Min.
4.5
Typ.
5.0
4.0
Max.
5.5
7.0
Unit
V
mA
mV
rms
mV
rms
mV
rms
mV
rms
4
U4289BM
4757A–AUDR–10/03
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