A29400 Series
512K X 8 Bit / 256K X 16 Bit CMOS 5.0 Volt-only,
Preliminary
Features
n
5.0V
±
10% for read and write operations
n
Access times:
- 55/70/90 (max.)
n
Current:
- 20 mA typical active read current
- 30 mA typical program/erase current
- 1
µA
typical CMOS standby
n
Flexible sector architecture
-
16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX7 sectors
-
8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX7 sectors
-
Any combination of sectors can be erased
-
Supports full chip erase
-
Sector protection:
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector
n
Top or bottom boot block configurations available
n
Embedded Erase Algorithms
- Embedded Erase algorithm will automatically erase
the entire chip or any combination of designated
sectors and verify the erased sectors
- Embedded Program algorithm automatically writes
and verifies bytes at specified addresses
n
Typical 100,000 program/erase cycles per sector
n
20-year data retention at 125°C
- Reliable operation for the life of the system
n
Compatible with JEDEC-standards
- Pinout and software compatible with single-power-
supply Flash memory standard
-
Superior inadvertent write protection
n
Data
Polling and toggle bits
-
Provides a software method of detecting completion
of program or erase operations
n
Erase Suspend/Erase Resume
-
Suspends a sector erase operation to read data from,
or program data to, a non-erasing sector, then
resumes the erase operation
n
Hardware reset pin (
RESET
)
-
Hardware method to reset the device to reading array
data
n
Package options
-
44-pin SOP or 48-pin TSOP (I)
Boot Sector Flash Memory
General Description
The A29400 is a 5.0 volt only Flash memory organized as
524,288 bytes of 8 bits or 262,144 words of 16 bits each. The
A29400 offers the
RESET
function. The 512 Kbytes of data
are further divided into eleven sectors for flexible sector erase
capability. The 8 bits of data appear on I/O
0
- I/O
7
while the
addresses are input on A1 to A17; the 16 bits of data appear
on I/O
0
~I/O
15
. The A29400 is offered in 44-pin SOP and 48-Pin
TSOP packages. This device is designed to be programmed in-
system with the standard system 5.0 volt VCC supply.
Additional 12.0 volt VPP is not required for in-system write or
erase operations. However, the A29400 can also be
programmed in standard EPROM programmers.
The A29400 has the first toggle bit, I/O
6
, which indicates
whether an Embedded Program or Erase is in progress, or it is
in the Erase Suspend. Besides the I/O
6
toggle bit, the A29400
has a second toggle bit, I/O
2
, to indicate whether the addressed
sector is being selected for erase. The A29400 also offers the
ability to program in the Erase Suspend mode. The standard
A29400 offers access times of 55, 70 and 90 ns, allowing high-
speed microprocessors to operate without wait states. To
eliminate bus contention the device has separate chip enable
(
CE
), write enable (
WE
) and output enable (
OE
) controls.
The device requires only a single 5.0 volt power supply for both
read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
The A29400 is entirely software command set compatible with
the JEDEC single-power-supply Flash standard. Commands are
written to the command register using standard microprocessor
write timings. Register contents serve as input to an internal
state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for
the programming and erase operations. Reading data out of the
device is similar to reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase command
sequence. This initiates the Embedded Erase algorithm - an
internal algorithm that automatically preprograms the array (if it is
not already programmed) before executing the erase operation.
During erase, the device automatically times the erase pulse
widths and verifies proper erase margin.
PRELIMINARY
(February, 2001, Version 0.1)
1
AMIC Technology, Inc.
A29400 Series
The host system can detect whether a program or erase
operation is complete by reading the I/O
7
(
Data
Polling) and
I/O
6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29400 is fully erased when
shipped from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the
sectors of memory. This can be achieved via programming
equipment.
The Erase Suspend feature enables the user to put erase on
hold for any period of time to read data from, or program
data to, any other sector that is not selected for erasure.
True background erase can thus be achieved.
Power consumption is greatly reduced when the device is
placed in the standby mode.
The hardware RESET pin terminates any operation in
progress and resets the internal state machine to reading
array data.
Pin Configurations
n
SOP
NC
RY/BY
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
I/O
0
I/O
8
I/O
1
I/O
9
I/O
2
I/O
10
I/O
3
I/O
11
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
I/O
15
(A-1)
I/O
7
I/O
14
I/O
6
I/O
13
I/O
5
I/O
12
I/O
4
VCC
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
n
TSOP (I)
10
11
12
13
14
15
16
17
18
19
20
21
22
A29400
9
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A29400V
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
I/O
15
(A-1)
I/O
7
I/O
14
I/O
6
I/O
13
I/O
5
I/O
12
I/O
4
VCC
I/O
11
I/O
3
I/O
10
I/O
2
I/O
9
I/O
1
I/O
8
I/O
0
OE
VSS
CE
A0
PRELIMINARY
(February, 2001, Version 0.1)
2
AMIC Technology, Inc.
A29400 Series
Block Diagram
RY/BY
VCC
VSS
I/O
0
- I/O
15
(A-1)
Sector Switches
Erase Voltage
Generator
State
Control
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data Latch
Input/Output
Buffers
RESET
WE
BYTE
Command
Register
CE
OE
STB
VCC Detector
Timer
Address Latch
Y-Decoder
Y-Gating
A0-A17
X-decoder
Cell Matrix
Pin Descriptions
Pin No.
A0 - A17
I/O
0
- I/O
14
I/O
15
I/O
15
(A-1)
A-1
Description
Address Inputs
Data Inputs/Outputs
Data Input/Output, Word Mode
LSB Address Input, Byte Mode
Chip Enable
Write Enable
Output Enable
Hardware Reset (N/A A294001)
Selects Byte Mode or Word Mode
Ready/
BUSY
- Output
Ground
Power Supply
CE
WE
OE
RESET
BYTE
RY/
BY
VSS
VCC
PRELIMINARY
(February, 2001, Version 0.1)
3
AMIC Technology, Inc.
A29400 Series
Absolute Maximum Ratings*
Ambient Operating Temperature . . . . . -55°C to + 125°C
Storage Temperature . . . . . . . . . . . . . . -65°C to + 125°C
Ground to VCC . . . . . . . . . . . . . . . . . . . . . . -2.0V to 7.0V
Output Voltage (Note 1) . . . . . . . . . . . . . . . -2.0V to 7.0V
A9,
OE
& RESET (Note 2) . . . . . . . . . . . -2.0V to 12.5V
All other pins (Note 1) . . . . . . . . . . . . . . . . . -2.0V to 7.0V
Output Short Circuit Current (Note 3) . . . . . . . . . . 200mA
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5V.
During voltage transitions, inputs may undershoot VSS
to -2.0V for periods of up to 20ns. Maximum DC
voltage on output and I/O pins is VCC +0.5V. During
voltage transitions, outputs may overshoot to VCC
+2.0V for periods up to 20ns.
2. Minimum DC input voltage on A9 pins is -0.5V. During
voltage transitions, A9,
OE
and RESET may overshoot
VSS to -2.0V for periods of up to 20ns. Maximum DC
input voltage on A9 and
OE
is +12.5V which may
overshoot to 13.5V for periods up to 20ns.
3. No more than one output is shorted at a time. Duration
of the short circuit should not be greater than one
second.
Operating Ranges
Commercial (C) Devices
Ambient Temperature (T
A
) . . . . . . . . . . . . . . 0°C to +70°C
VCC Supply Voltages
VCC for
±
10% devices . . . . . . . . . . . . . . +4.5V to +5.5V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
Device Bus Operations
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location. The
register is composed of latches that store the commands,
along with the address and data information needed to
execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine
outputs dictate the function of the device. The appropriate
device bus operations table lists the inputs and control
levels required, and the resulting output. The following
subsections describe each of these operations in further
detail.
Table 1. A29400 Device Bus Operations
Operation
Read
Write
CMOS Standby
TTL Standby
Output Disable
Hardware Reset
Temporary Sector
Unprotect (See Note)
CE
L
L
VCC
±
0.5 V
H
L
X
X
OE
L
H
X
X
H
X
X
WE
H
L
X
X
H
X
X
RESET
H
H
VCC
±
0.5 V
H
H
L
V
ID
A0 - A17
A
IN
A
IN
X
X
X
X
A
IN
I/O
0
- I/O
7
D
OUT
D
IN
High-Z
High-Z
High-Z
High-Z
D
IN
I/O
8
- I/O
15
BYTE
=V
IH
D
OUT
D
IN
High-Z
High-Z
High-Z
High-Z
D
IN
BYTE
=V
IL
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5V, X = Don't Care, D
IN
= Data In, D
OUT
= Data Out, A
IN
= Address In
Note:
See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information.
PRELIMINARY
(February, 2001, Version 0.1)
4
AMIC Technology, Inc.
A29400 Series
Word/Byte Configuration
The
BYTE
pin determines whether the I/O pins I/O
15
-I/O
0
operate in the byte or word configuration. If the
BYTE
pin
is set at logic ”1”, the device is in word configuration, I/O
15
-
I/O
0
are active and controlled by
CE
and
OE
.
If the
BYTE
pin is set at logic “0”, the device is in byte
configuration, and only I/O
0
-I/O
7
are active and controlled
by
CE
and
OE
. I/O
8
-I/O
14
are tri-stated, and I/O
15
pin is
used as an input for the LSB(A-1) address function.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O
7
- I/O
0
. Standard read cycle timings and I
CC
read
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section
for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs
are placed in the high impedance state, independent of the
OE
input.
The device enters the CMOS standby mode when the
CE
& RESET pins are both held at V
CC
±
0.5V. (Note that this
is a more restricted voltage range than V
IH
.) The device
enters the TTL standby mode when
CE
is held at V
IH
,
while RESET is held at VCC±0.5V. The device requires the
standard access time (t
CE
) before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
I
CC3
in the DC Characteristics tables represents the standby
current specification.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the
CE
and
OE
pins to V
IL
.
CE
is the power control and
selects the device.
OE
is the output control and gates
array data to the output pins.
WE
should remain at V
IH
all
the time during read operation. The internal state machine
is set for reading array data upon device power-up, or after
a hardware reset. This ensures that no spurious alteration
of the memory content occurs during the power transition.
No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
See "Reading Array Data" for more information. Refer to
the AC Read Operations table for timing specifications and
to the Read Operations Timings diagram for the timing
waveforms, l
CC1
in the DC Characteristics table represents
the active current specification for reading array data.
Output Disable Mode
When the
OE
input is at V
IH
, output from the device is
disabled. The output pins are placed in the high impedance
state.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive
WE
and
CE
to V
IL
, and
OE
to V
IH
. An erase operation can erase one
sector, multiple sectors, or the entire device. The Sector
Address Tables indicate the address range that each sector
occupies. A "sector address" consists of the address inputs
required to uniquely select a sector. See the "Command
Definitions" section for details on erasing a sector or the
entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can
then read autoselect codes from the internal register (which
is separate from the memory array) on I/O
7
- I/O
0
. Standard
read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
I
CC2
in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
RESET
: Hardware Reset Pin
The RESET pin provides a hardware method of resetting
the device to reading array data. When the system drives
the RESET pin low for at least a period of t
RP
, the device
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the RESET pulse. The device also resets
the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once
the device is ready to accept another command sequence,
to ensure data integrity.
The RESET pin may be tied to the system reset circuitry.
A system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
Refer to the AC Characteristics tables for RESET
parameters and diagram.
PRELIMINARY
(February, 2001, Version 0.1)
5
AMIC Technology, Inc.
RF/Wirelessly
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