ASAHI KASEI
[AKD4380]
AKD4380
Evaluation board Rev.A for AK4380
GENERAL DESCRIPTION
The AKD4380 is an evaluation board for AK4380, which is 96kHz sampling 24Bit∆ΣDAC.
AKD4380 has the interface with AKM’s wave generator using ROM data and with AKM’s A/D converter
evaluation boards. Therefore, it is easy to evaluate the AK4380. The AKD4380 also has the digital audio
interface and can achieve the interface with digital audio systems via opt-connector or RCA connector.
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Ordering guide
AKD4380
---
Evaluation board for AK4380
FUNCTION
•
Compatible with 2 types of interface
-Direct interface with AKM’s A/D converter evaluation boards (539X,535X)
,and direct interface with a signal generator (AKD43XX)
- On-board CS8414 as DIR which accepts optical or RCA input.
•
BNC connector for an external clock input by 10 pin Hearder.
O p tic a l
In p u t
C S 8414
(DIR )
Lch
10p in H e a d e r
R O M D a ta
or
A / in p u t
D
A K 4380
Rch
E x tern a l
C lo c k
C lo c k
G e n e rato r
Figure 1. AKD4380 Block Diagram
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[AKD4380]
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Analog output
Analog signal is output through BNC connectors on the board. And the output level of AK4380 is 3.45Vpp.
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Operation sequence
1) Set up the power supply lines.
[VA] (red)
= 4.5
∼
5.5V
[VD] (red)
= 4.5
∼
5.5V
[AGND] (black) = 0V
[DGND] (black) = 0V
Each supply line should be distributed from the power supply unit.
2) Set up the evaluation mode, jumper pins and DIP switches.
(See the followings.)
3) Power on.
The AK4380 should be reset once bringing upon power-up
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Evaluation mode
Applicable evaluation modes
1) DIR (Optical Link and RCA) (default)
2) Using ROM data (AK43XX)
3) Using AKM’s evaluation board for ADC
4) Feeding all signals from external
1) DIR(Optical Link)
PORT3(TORX176) or J3(RCA) is used. All clock are supplied from CS8414(DIR). DIR generates MCLK,
BICK, LRCK and SDATA from the received data through optical connector (TORX176) or RCA connector.
Used for the evaluation using CD test disk. Nothing should be connected to PORT2. In case of using optical
connector (TORX176), select “OPT” on JP14(DIR/RX). In case of using RCA connector, select “RX”.
JP3
BICK
JP4
LRCK
JP9
SDTI
JP10
DIR_DATA
JP11
DIR
JP12
MCLK
JP13
XTE
ADC
DIR
ADC
DIR
GND
DATA
VD
GND
EXT
JP13
XTE
EXT
XTL
XTL
DIR
2) Ideal sine wave generated by ROM data
Connect the AKD43XX with PORT2(ADC/ROM). AKD4380 sends MCLK to AKD43XX, and receives LRCK,
BICK and SDATA. In case of using external master clock through a BNC connector, select “BNC” on
JP12(MCLK) and short JP13(XTE).
JP3
BICK
JP4
LRCK
JP9
SDTI
JP10
DIR_DATA
JP11
DIR
JP12
MCLK
ADC
DIR
ADC
DIR
GND
DATA
VD
GND
DIR
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ASAHI KASEI
[AKD4380]
3) Using AKM’s evaluation board for ADC
To evaluate AK4380 with analog input, the AKM’s evaluation board for ADC can be used. MCLK, BICK and
LRCK are supplied from clock generator on the AKD4380, and analog signal is A/D converted and send to
AKD4380 through PORT2(ADC/ROM). In case of using external master clock through a BNC connector, select
“BNC” on JP12(MCLK) and short JP13(XTE).
JP3
BICK
JP4
LRCK
JP9
SDTI
JP10
DIR_DATA
JP11
DIR
JP12
MCLK
JP13
XTE
ADC
DIR
ADC
DIR
GND
DATA
VD
GND
EXT
JP13
XTE
EXT
XTL
XTL
DIR
4) Feeding all signals from external
Under the following set-up, all external signals can be fed through POTR2.
JP3
BICK
JP4
LRCK
JP9
SDTI
JP10
DIR_DATA
JP11
DIR
JP12
MCLK
ADC
DIR
ADC
DIR
GND
DATA
VD
GND
DIR
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Clock (MCLK,BICK,LRCK) set up
In case of using evaluation mode 1), JP9,10 and 17 should be set up as follows.
They need no care for other evaluation mode.
MCLK
128fs
256fs
JP5
(X_MCLK)
256/128
256/128
JP8
(X_LRCK)
LR_128
BICK
JP7
(X_BICK)
64fs/32fs
128fs/64fs
32fs
64fs/32fs
128fs/64fs
32fs
64fs/32fs
128fs/64fs
512fs
512
32fs
64fs
LR_256/512
32fs
64fs
128fs
LR_256/512
32fs
64fs
128fs
Table 1. Clock set up
default
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[AKD4380]
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DIP switch set up
[SW4](MODE1): No.1 to 2 set the mode of AK4380 and No.3 to 5 set the mode of CS8414.
No.
1
2
3
4
5
Pin
DFS0
DIF0
M2
M1
M0
OFF
ON
Normal speed
Double speed
24bit, MSB justified
I2S
Digital interface format of CS8414
(See table 4.)
(Note)
Table 2. SW3 set-up
(Note: M2-0 should be selected at only evaluation mode 1.
In other mode, these should be “OFF”.)
3
4
5
6
7
8
Format
DIF0 DIF1 DIF2 M2
M1
M0
16bit, LSB justified
0
0
0
1
0
1
20bit, LSB justified
1
0
0
-
-
-
24bit, MSB justified
0
1
0
0
0
0
I2S
1
1
0
0
1
0
24bit, LSB justified
0
0
1
-
-
-
Table 3. Digital interface format set-up (1=ON, 0=OFF)
(CS8414 does not correspond to 20/24bit LSB justified format.)
JP6
BICK2
THR
-
INV
THR default
-
Mode
0
1
2
3
4
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Other jumper pins set up
[JP1] (GND): Analog ground and digital ground
open: separated <default>
short: AGND and DGND are connected.
[JP2] (DZF) Mute circuit
ON: Used . Analog output are muted when DZF=”H”.
OFF: Not used. <default>
[JP6] (BICK_ PHASE): Phase of BCLK
THR: BICK is coincides with AK4380. <default>
INV: BICK is inverted.
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The function of the toggle SW.
[SW1](PDN):
Resets the AK4380. Keep “H” during normal operation.
[SW2](SMUTE): Soft mute of AK4380. Bring “H” when using soft mute.
[SW3](P/S):
H: parallel mode.
L: serial mode.
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Indication for LED
[LED1] (VERF): Monitor VERF pin of the CS8414. LED turns on when some error has occurred to CS8414.
[LED2]: (PREM): Indicate whether the input data of CS8414 is pre-emphasized or not.
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Serial control mode
The AK4380 can be controlled via the printer port (parallel port) of IBM-AT
compatible PC. Connect PORT1(up-I/F) with PC by 10-line flat cable
packed with the AKD4380.
Take care of the direction of connector. There is a mark at 1pin.
The pin layout of PORT1 is as Figure 2.
10
PORT1
up-I/F
9
CSN
CCLK
CDTI
2
1
Figure 2. PORT1 pin layout
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ASAHI KASEI
[AKD4380]
MEASUREMENT RESULTS
[Measurement condition]
•
Measurement unit: Audio Precision System Two Cascade
•
MCLK
: 256fs
•
BICK
: 64fs
•
fs
: 44.1kHz, 96kHz
•
BW
: 10Hz∼20kHz (fs=44.1kHz), 10Hz∼40kHz (fs=96kHz)
•
Bit
: 24bit
•
Power Supply
: VDD=5V
•
Interface
: DIR (fs=44.1kHz, 96kHz)
•
Temperature
: Room
Parameter
S/(N+D)
DR
S/N
Input signal
1kHz, 0dB
1kHz, -60dB
no signal
Measurement filter
20kLPF
22kLPF
22kLPF, A-weighted
22kLPF
22kLPF, A-weighted
Measurement filter
40kLPF
40kLPF
22kLPF, A-weighted
40kLPF
22kLPF, A-weighted
fs=44.1kHz
94.0dB
97.2dB
100.0dB
97.2dB
100.0dB
fs=96kHz
92.3dB
94.5dB
97.2dB
94.5dB
97.2dB
Parameter
S/(N+D)
DR
S/N
Input signal
1kHz, 0dB
1kHz, -60dB
no signal
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FPGA/CPLD
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